Ryan Keily Roderick

US Patent:

20110074457, Mar 31, 2011

Filed:

Jan 17, 2010

Appl. No.:

12/688903

Inventors:

Ryan B. Roderick - San Jose CA, US
Ronald D. Kimmel - Fremont CA, US

International Classification:

G01R 31/02
G01R 31/20

US Classification:

32475602, 32475702, 32475605

Abstract:

An improved efficiency system for testing electronic components in a motherboard/daughterboard assembly in which the daughterboard is mounted in spaced parallel relationship the to motherboard includes one or more device-under-test socket sub-assemblies having a test socket thereon for receiving a device-under-test and a connector component for disengagable connection to a complementary connector component on the daughterboard with the socket sub-assembly effecting interengagement of the complementary connector component on the daughterboard via an opening in the motherboard to allow ready access to the test socket for temporary installation, testing, and removal of a device-under-test.