Sadagopan Srinivasan

US Patent:

8649262, Feb 11, 2014

Filed:

Sep 30, 2008

Appl. No.:

12/241619

Inventors:

Sadagopan Srinivasan - Hillsboro OR, US
Michael W. Leddige - Beaverton OK, US
Bin Li - Princeton NJ, US
Michael Espig - Newberg OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 12/26

US Classification:

370229

Abstract:

According to some embodiments, first and second processing elements may be provided on a die, and there may be a plurality of potential communication links between the first and second processing elements. Moreover, control logic may be provided on the die to dynamically activate at least some of the potential communication links (e. g. , based on a current bandwidth appropriate between the first and second processing elements).

US Patent:

20110113198, May 12, 2011

Filed:

Nov 12, 2009

Appl. No.:

12/590651

Inventors:

Liqun Cheng - Hillsboro CA, US
Zhen Fang - Portland CA, US
Jeffrey Wilder - Dupont WA, US
Sadagopan Srinivasan - Hillsboro OR, US
Ravishankar Iyer - Portland CA, US
Donald Newell - Portland OR, US

International Classification:

G06F 12/08
G06F 12/00

US Classification:

711128, 711E12001, 711E12018

Abstract:

The present invention discloses a method comprising: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a source of the request for data; if the source is an input/output device, masking off P ways in a cache; and allocating ways in filling the cache. The method further includes extending cache allocation logic to control a tag comparison operation by using a bit to provide a hint from IO devices that certain ways will not have requested data.

US Patent:

20120079235, Mar 29, 2012

Filed:

Sep 25, 2010

Appl. No.:

12/890653

Inventors:

Ravishankar Iyer - Portland OR, US
Sadagopan Srinivasan - Hillsboro OR, US
Li Zhao - Beaverton OR, US
Rameshkumar G. Illikkal - Portland OR, US

International Classification:

G06F 9/305
G06F 9/46

US Classification:

712 30, 718108, 718102, 712E09018

Abstract:

Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.

US Patent:

20120173907, Jul 5, 2012

Filed:

Dec 30, 2011

Appl. No.:

13/341657

Inventors:

Jaideep MOSES - Portland OR, US
Rameshkumar G. Illikkal - Portland OR, US
Ravishankar Iyer - Portland OR, US
Jared E. Bendt - Hillsboro OR, US
Sadagopan Srinivasan - Hillsboro OR, US
Andrew J. Herdrich - Hillsboro OR, US
Ashish V. Choubal - Austin TX, US
Avinash N. Ananthakrishnan - Hillsboro OR, US
Vijay S.R. Degalahal - Bangalore, IN

International Classification:

G06F 1/32

US Classification:

713321

Abstract:

Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.

US Patent:

20180329478, Nov 15, 2018

Filed:

Jul 24, 2018

Appl. No.:

16/043738

Inventors:

- Santa Clara CA, US
Rameshkumar G. Illikkal - Folsom CA, US
Ravishankar Iyer - Portland OR, US
Sadagopan Srinivasan - Hillsboro OR, US
Jaideep Moses - Portland OR, US
Srihari Makineni - Hillsboro OR, US

International Classification:

G06F 1/32
H04W 88/02
H04W 52/02
G06F 12/084
G06F 9/4401
G06F 9/50
G06F 13/24

Abstract:

In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

US Patent:

20180039518, Feb 8, 2018

Filed:

Aug 2, 2016

Appl. No.:

15/226384

Inventors:

- San Diego CA, US
Sadagopan Srinivasan - Austin TX, US
Thomas Andrew Hartin - Austin TX, US

International Classification:

G06F 9/50
G06F 9/455
G06F 9/52

Abstract:

In an illustrative example, a system includes a resource and a first processor. The first processor is configured to access the resource based on a first physical address space and to generate a request for access to the resource. The request has a first format. The system further includes a second processor configured to access the resource based on a second physical address space. The system also includes a device coupled to the resource and to the first processor. The device is configured to receive the request, to generate a message having a second format based on the request, to send the message to the resource, and to provide a reply to the request to the first processor.

US Patent:

20170371564, Dec 28, 2017

Filed:

Jun 28, 2016

Appl. No.:

15/195006

Inventors:

- Sunnyvale CA, US
Sadagopan Srinivasan - Austin TX, US
Daniel L. Bouvier - Austin TX, US

International Classification:

G06F 3/06

Abstract:

Methods and apparatus monitor memory access activities of non-real-time processing engines to determine time intervals when the memory access activities are low. When such time intervals are found, the methods and apparatus perform burst memory access control for real-time processing engines by bursting data from a memory to a burst memory buffer, or from the burst memory buffer to the memory, to allow fast data access by the real-time processing engines.

US Patent:

20170337084, Nov 23, 2017

Filed:

May 18, 2016

Appl. No.:

15/157942

Inventors:

- San Diego CA, US
Raghuram S. Tupuri - Austin TX, US
Sadagopan Srinivasan - Austin TX, US
Thomas Andrew Hartin - Austin TX, US

International Classification:

G06F 9/50

Abstract:

An apparatus includes a set of one or more processing cores, a thread dispatcher, and an event register of a first compute unit. The set of one or more processing cores is configured to execute a set of threads. The thread dispatcher is coupled to the set of one or more processing cores and is configured to select threads of the set of threads for execution by the set of one or more processing cores. The thread dispatcher is further configured to refrain from selecting a first thread of the set of threads for execution in response to a first value of one or more bits of the event register and to select the first thread for execution in response to a second value of the one or more bits.