Sagar Rajiv Vaze

age ~33

from San Jose, CA

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Also known as:
  • Sagar R Vaze
Connected to:

Sagar Vaze Phones & Addresses

  • San Jose, CA
  • Santa Clara, CA
  • Cupertino, CA
  • New York, NY
  • Sioux Falls, SD

Work

  • Company:
    Fairchild semiconductor
    Jun 2014
  • Position:
    Summer internship - fairchild semiconductor

Education

  • School / High School:
    Columbia University, School of Engineering and Applied Science- New York, NY
    2013
  • Specialities:
    M.S. in Electrical Engineering

Skills

Analog Circuit Design • RF Design • Mixed-Signal Design • FPGA Design • Cadence Virtuoso • Agilent ADS • Xilinx ISE • Altera Quartus • IE3D • CppSim • HSPICE • PCB Design • C • C++ • Python • PHP • JavaScript • MATLAB • Verilog • Verilog-AMS

Resumes

Sagar Vaze Photo 1

Electrical Engineer

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Location:
Cupertino, CA
Industry:
Consumer Electronics
Work:
Apple
Electrical Engineer
Fairchild Semiconductor Jun 2014 - Sep 2014
Analog and Mixed-Signal Design Intern
Columbia University In the City of New York Sep 2013 - May 2014
Research Assistant
Technische Universität München May 2012 - Jul 2012
Summer Research Assistant
Suzlon Wind Energy A/S May 2011 - Jul 2011
Summer Intern
Education:
Columbia University In the City of New York 2013 - 2014
Masters, Electronics Engineering Columbia Engineering 2013 - 2014
Masters, Applied Science, Engineering, Electronics Engineering, Electronics Indian Institute of Technology, Madras 2009 - 2013
Bachelors, Bachelor of Technology, Electronics Engineering, Electronics Dr. Kalmadi Shamrao High School 2007
Skills:
Matlab
C++
Integrated Circuit Design
Python
Electrical Engineering
Analog
Vhdl
C
Verilog
Algorithms
Java
Cadence Virtuoso
Fpga
Latex
Cmos
Php
Xilinx Ise
Mixed Signal
Verilog Ams
Electronics Hardware Design
Web Development
Very Large Scale Integration
Integrated Circuits
Radio Frequency
Semiconductors
Digital Signal Processing
Circuit Design
Firmware
Automation
Data Analysis
Data Mining
Data Structures
Languages:
Marathi
English
Hindi
Sagar Vaze Photo 2

Sagar Vaze

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Sagar Vaze Photo 3

Sagar Vaze

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Sagar Vaze Photo 4

Sagar Vaze San Jose, CA

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Work:
Fairchild Semiconductor

Jun 2014 to 2000
Summer Internship - Fairchild Semiconductor Columbia University
New York, NY
Sep 2013 to May 2014
Research Assistant Institute for EDA, TU-Munich
Mnchen
May 2012 to Jul 2012
Summer Research Assistant
Education:
Columbia University, School of Engineering and Applied Science
New York, NY
2013 to 2014
M.S. in Electrical Engineering Indian Institute of Technology Madras
Chennai, Tamil Nadu
2009 to 2013
B.Tech. in Electrical Engineering
Skills:
Analog Circuit Design, RF Design, Mixed-Signal Design, FPGA Design, Cadence Virtuoso, Agilent ADS, Xilinx ISE, Altera Quartus, IE3D, CppSim, HSPICE, PCB Design, C, C++, Python, PHP, JavaScript, MATLAB, Verilog, Verilog-AMS

Us Patents

  • Self-Capacitance And Mutual Capacitance Touch Sensor Panel Architecture

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  • US Patent:
    20230011279, Jan 12, 2023
  • Filed:
    May 26, 2022
  • Appl. No.:
    17/804237
  • Inventors:
    - Cupertino CA, US
    Jean-Marie BUSSAT - San Jose CA, US
    Robert Leo SHERIDAN - Sunnyvale CA, US
    Sagar Rajiv VAZE - San Jose CA, US
  • International Classification:
    G06F 3/044
    G06F 3/041
    G06F 3/047
  • Abstract:
    A touch sensor panel includes a first set of touch electrodes configured to operate as drive lines and that are disposed in a first layer of the touch sensor panel. The touch sensor panel also includes a second set of touch electrodes configured to operate as sense lines and that are disposed in a second layer of the touch sensor panel, different than the first layer of the touch sensor panel, such that one or more mutual capacitance touch nodes are formed by the first set of touch electrodes and the second set of touch electrodes. The touch sensor panel also includes a third set of touch electrodes configured to operate as self-capacitance electrodes and that are disposed in the first layer or the second layer of the touch sensor panel.

  • Differential Drive And Sense For Touch Sensor Panel

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  • US Patent:
    20210373711, Dec 2, 2021
  • Filed:
    May 20, 2021
  • Appl. No.:
    17/326249
  • Inventors:
    - Cupertino CA, US
    Amit NAYYAR - Saratoga CA, US
    Joseph Kurth REYNOLDS - San Jose CA, US
    Sagar Rajiv VAZE - San Jose CA, US
    Marduke YOUSEFPOR - San Jose CA, US
  • International Classification:
    G06F 3/044
    G06F 3/041
  • Abstract:
    Touch sensor panels (or touch screens) can improve signal-to-noise ratio (SNR) using touch electrode patterns for differential drive and/or differential sense techniques. In some examples, a touch sensor panel can include a two-dimensional array of touch nodes formed from a plurality of touch electrodes. Each column (or row) of touch nodes can be driven with a plurality of drive signals. For example, a first column (or row) of touch nodes can be driven by a first drive signal applied to one or more first touch nodes in the first column (or row) and a second drive signal applied to a one or more second touch nodes of the first column (or row). In some examples, the first drive signal and the second drive signal can be complimentary drive signals. In some examples, each row (or column) of touch electrodes can be sensed by differential sense circuitry.

  • Self-Capacitance And Mutual Capacitance Touch-Sensor Panel Architecture

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  • US Patent:
    20200371636, Nov 26, 2020
  • Filed:
    Aug 10, 2020
  • Appl. No.:
    16/989645
  • Inventors:
    - Cupertino CA, US
    Jean-Marie BUSSAT - San Jose CA, US
    Robert Leo SHERIDAN - Sunnyvale CA, US
    Sagar Rajiv VAZE - Sunnyvale CA, US
  • International Classification:
    G06F 3/041
    G06F 3/044
    G06F 3/047
  • Abstract:
    A touch sensor panel is disclosed. The touch sensor panel includes a first set of touch electrodes configured to operate as drive lines and that are disposed in a first layer of the touch sensor panel. The touch sensor panel also includes a second set of touch electrodes configured to operate as sense lines and that are disposed in a second layer of the touch sensor panel, different than the first layer of the touch sensor panel, such that one or more mutual capacitance touch nodes are formed by the first set of touch electrodes and the second set of touch electrodes. The touch sensor panel also includes a third set of touch electrodes configured to operate as self-capacitance electrodes and that are disposed in the first layer or the second layer of the touch sensor panel.

  • Diamond Based Touch Sensor Panel Architectures

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  • US Patent:
    20200103994, Apr 2, 2020
  • Filed:
    Aug 26, 2019
  • Appl. No.:
    16/551698
  • Inventors:
    - Cupertino CA, US
    Sagar Rajiv VAZE - Sunnyvale CA, US
  • International Classification:
    G06F 3/044
    G06F 1/16
    G06F 3/045
  • Abstract:
    A touch sensor panel including a first set of touch electrodes configured to operate as drive electrodes and a second set of touch electrodes configured to operate as sense electrodes. The first set of touch electrodes being disposed within gaps between the second set of touch electrodes, and a given row or column of touch electrodes of the second set of touch electrodes includes a plurality of subsets of touch electrodes that are separately addressable by touch sensing circuitry.

  • Self-Capacitance And Mutual Capacitance Touch-Sensor Panel Architecture

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  • US Patent:
    20190056834, Feb 21, 2019
  • Filed:
    Aug 15, 2018
  • Appl. No.:
    15/998425
  • Inventors:
    - Cupertino CA, US
    Jean-Marie Bussat - San Jose CA, US
    Robert Leo Sheridan - Sunnyvale CA, US
    Sagar Rajiv Vaze - Cupertino CA, US
  • International Classification:
    G06F 3/041
    G06F 3/044
    G06F 3/047
  • Abstract:
    A touch sensor panel is disclosed. The touch sensor panel includes a first set of touch electrodes configured to operate as drive lines and that are disposed in a first layer of the touch sensor panel. The touch sensor panel also includes a second set of touch electrodes configured to operate as sense lines and that are disposed in a second layer of the touch sensor panel, different than the first layer of the touch sensor panel, such that one or more mutual capacitance touch nodes are formed by the first set of touch electrodes and the second set of touch electrodes. The touch sensor panel also includes a third set of touch electrodes configured to operate as self-capacitance electrodes and that are disposed in the first layer or the second layer of the touch sensor panel.

  • High Aspect Ratio Capacitive Sensor Panel

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  • US Patent:
    20170090622, Mar 30, 2017
  • Filed:
    Aug 4, 2016
  • Appl. No.:
    15/228942
  • Inventors:
    - Cupertino CA, US
    Sudip MONDAL - Santa Clara CA, US
    Sagar Rajiv VAZE - Cupertino CA, US
    Albert LIN - Cupertino CA, US
    Qian ZHAO - Santa Clara CA, US
    Chun-Hao TUNG - San Jose CA, US
    Sunggu KANG - San Jose CA, US
    John Z. ZHONG - Saratoga CA, US
  • International Classification:
    G06F 3/044
  • Abstract:
    High aspect ratio touch sensor panels are disclosed in which multiple row electrode blocks can be formed in a single row within an active area of the touch sensor panel, each row electrode block including a plurality of vertically adjacent row electrodes, or in some instances only one row electrode. In addition, each column electrode can be separated into multiple column electrode segments, each column electrode segment being vertically oriented and formed in a different column. The column electrode segments associated with any one column electrode can be spread out so that each of these column electrodes segments can be co-located and associated with a different row electrode block.

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Vivek Anand, Vikram Bhagat, Shrirang Purohit, Sushant Charde, Archana Manjre
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