Said E Abdelli

US Patent:

7113755, Sep 26, 2006

Filed:

Aug 19, 2003

Appl. No.:

10/644630

Inventors:

Said E. Abdelli - Minneapolis MN, US

Assignee:

Honeywell International, Inc. - Morristown NJ

International Classification:

H01Q 11/12
H04B 1/04
H04B 1/28

US Classification:

455118, 455326, 455333

Abstract:

A mixer circuit in accordance with an embodiment of the invention includes a first mixer stage including first and second transmission gates, and a second mixer stage including third and fourth transmission gates. The mixer further includes a first base band signal terminal coupled with the first and second transmission gates and a second base band signal terminal coupled with the third and fourth transmission gates. The mixer circuit processes signals so as to mix a base band signal communicated to the first and second base band signal terminals with a differential LO signal communicated to first and second LO signal terminals to create a first mixed differential signal. Alternatively, the mixer extracts a base band signal from a mixed signal communicated to the first and second mixed signal terminals signal using the LO signal communicated to the first and second LO signal terminals.

US Patent:

7113756, Sep 26, 2006

Filed:

Jun 3, 2005

Appl. No.:

11/144343

Inventors:

Said E. Abdelli - Minneapolis MN, US

Assignee:

Honeywell International, Inc. - Morristown NJ

International Classification:

H01Q 11/12
H04B 1/04
H04B 1/28

US Classification:

455118, 455326, 455333

Abstract:

A mixer circuit is disclosed that includes a first mixer stage including first and second transmission gates. The mixer circuit also includes a second mixer stage including third and fourth transmission gates. The mixer further includes a first base band signal terminal coupled with the first and second transmission gates and a second base band signal terminal coupled with the third and fourth transmission gates. The mixer circuit processes signals so as to mix a base band signal communicated to the first and second base band signal terminals with a differential LO signal communicated to first and second LO signal terminals to create a first mixed differential signal. Alternatively, the mixer extracts a base band signal from a mixed signal communicated to the first and second mixed signal terminals signal using the LO signal communicated to the first and second LO signal terminals.

US Patent:

7279909, Oct 9, 2007

Filed:

Apr 20, 2006

Appl. No.:

11/408870

Inventors:

Said E. Abdelli - Minneapolis MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G01R 27/08

US Classification:

324705, 324656

Abstract:

Signal coincidence detection circuits and methods implemented in such circuits are disclosed. An example signal coincidence detection circuit includes a first differential transistor pair, a second differential transistor pair coupled with the first differential transistor pair and a third differential transistor pair coupled with the first differential transistor pair in parallel with the second differential transistor pair. The circuit also includes a first input signal terminal coupled with the first, second and third differential transistor pairs, wherein, in operation, the first input signal terminal receives a first input signal that is communicated to the first, second and third differential transistor pairs. The circuit further includes a second input signal terminal coupled with the first, second and third differential transistor pairs, wherein, in operation, the second input signal terminal receives a second input signal that is communicated to the first, second and third differential transistor pairs. The circuit additionally includes a current source coupled with the first differential transistor pair, where, in operation, a plurality of currents of the second and third differential transistor pairs are combined such that the combined currents indicate whether or not coincidence between the first and second input signals exists.

US Patent:

7355466, Apr 8, 2008

Filed:

Jan 26, 2006

Appl. No.:

11/341350

Inventors:

Said E. Abdelli - Minneapolis MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 7/16

US Classification:

327356, 327359, 455326

Abstract:

Mixer circuits with direct-current bias are disclosed. An example embodiment of such a mixer includes a first differential transistor pair and a second differential transistor pair. The example mixer also includes first and second local oscillator signal terminals and first and second mixed signal terminals. The first and second local oscillator signal terminals are coupled with the first and second differential transistor pairs. The first mixed signal terminal is coupled with the first differential pair and the second mixed signal terminal is coupled with the second differential pair. The mixer further includes first and second baseband signal terminals, where each baseband signal terminal is coupled with the first differential pair and the second differential pair. The mixer still further includes a first current source and a second current source. The first current source is coupled with the first differential pair and the first mixed signal terminal, and provides a first direct-current bias to the first differential pair.

US Patent:

7446608, Nov 4, 2008

Filed:

Feb 16, 2006

Appl. No.:

11/355673

Inventors:

Said E. Abdelli - Minneapolis MN, US

Assignee:

Honeywell Inernational Inc. - Morristown NJ

International Classification:

H03F 3/45

US Classification:

330254, 330253

Abstract:

Variable gain amplifier (VGA) circuits and methods implemented in such circuits are disclosed. An example VGA circuit includes a differential transistor pair for receiving a differential input signal. The differential transistor pair, in operation, conducts a substantially constant current over a linear operating range of the variable gain amplifier circuit. The VGA circuit also includes a current source that is coupled with the differential transistor pair. The current source, in operation, provides the substantially constant current to the differential transistor pair. The VGA circuit further includes a variable resistance circuit coupled with the differential transistor pair. In operation, a resistance of the variable resistance circuit is adjusted such that a gain of the variable gain amplifier circuit is adjusted. Further, in operation, the VGA circuit produces a differential output signal, the differential output signal being an amplified version of the differential input signal.

US Patent:

7688110, Mar 30, 2010

Filed:

Jan 7, 2008

Appl. No.:

11/970327

Inventors:

Jeffrey D. Loukusa - Hamel MN, US
Said E. Abdelli - Minneapolis MN, US

Assignee:

Honeywell International, Inc. - Morristown NJ

International Classification:

H03K 19/0175

US Classification:

326 66, 326 73, 326 77

Abstract:

A system for providing a CMOS I/O circuit design that may replace existing bipolar I/O circuitry, and thus behave in substantially the same manner as bipolar I/O circuitry. Thus, an I/O circuit using a standard CMOS process is made that mimics operation of an ECL I/O circuit created using bipolar transistors. The CMOS input circuitry can receive input signals from an ECL output circuit, so as to mimic traditional ECL input circuitry. The CMOS output circuitry can output signals to an ECL input circuit, so as to mimic traditional ECL output circuitry. The CMOS I/O circuitry is designed to mimic the temperature dependent signals level, as present within traditional ECL I/O circuitry.

US Patent:

8085091, Dec 27, 2011

Filed:

Jan 27, 2010

Appl. No.:

12/694734

Inventors:

Said Abdelli - Minneapolis MN, US
Jeffrey Kriz - Eden Prairie MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H03F 3/45

US Classification:

330254

Abstract:

Systems, methods, and devices provided herein are directed to improvements in gain control amplifiers that receive an input signal and generate an output signal with a selectively variable gain. A differential amplified gain stage receives an input signal and scales the input signal to generate a scaled signal. A gain adjust stage receives the scaled signal and an adjust signal and adjusts an amplitude of the scaled signal based on the adjust signal to generate an adjusted scaled signal. The adjusted scaled signal has a substantially constant impedance regardless of value of the adjust signal.

US Patent:

8098097, Jan 17, 2012

Filed:

Dec 23, 2009

Appl. No.:

12/646329

Inventors:

Said Abdelli - Minneapolis MN, US
Jeffrey Kriz - Eden Prairie MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H03F 3/45

US Classification:

330254, 330301

Abstract:

Systems, methods, and devices for receiving a differential input signal and generating a non-differential output signal are described herein. For example, an RF buffer is described that includes first and second transistor elements. The first transistor element receives a first polarity signal of a differential signal and drives a non-differential output of the RF buffer. A second transistor element receives a second polarity signal of the differential signal and drives the non-differential output of the RF buffer. The first and second transistor elements substantially simultaneously drive the non-differential output of the RF buffer.