Sameer Dhruva Halepete

age ~53

from San Jose, CA

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Also known as:
  • Sameer D Halepete
  • Sameer Te Halepete
  • Sameer S Halepete
Phone and address:
5746 Country Club Pkwy, San Jose, CA 95138
4087687260
Related to:
Connected to:

Sameer Halepete Phones & Addresses

  • 5746 Country Club Pkwy, San Jose, CA 95138 • 4087687260
  • 5882 Gleneagles Dr, San Jose, CA 95138 • 4082749492
  • Sunnyvale, CA
  • Stanford, CA
  • Santa Clara, CA
  • Mountain View, CA
  • 5746 Country Club Pkwy, San Jose, CA 95138

Work

  • Position:
    Installation, Maintenance, and Repair Occupations

Education

  • Degree:
    Associate degree or higher

Resumes

Sameer Halepete Photo 1

Vice President Of Vlsi Engineering

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Location:
Santa Clara, CA
Industry:
Semiconductors
Work:
NVIDIA Corporation since Jan 2007
Vice President of VLSI Engineering
NVIDIA Foundation 2007 - 2009
Member of Board of Directors
NVIDIA Corporation Oct 2002 - Jan 2007
Director of HW Engineering
Transmeta Corporation Feb 1996 - Oct 2002
Director of CPU Design
Sun Microsystems Inc. Apr 1995 - Feb 1996
Member of Technical Staff
Education:
Stanford University Sep 1993 - Apr 1995
MSEE, Electrical Engineering IIT Bombay Aug 1989 - Apr 1993
BSEE, Electical Engineering
Skills:
Asic
Soc
Semiconductors
Processors
Vlsi
Cmos
Microprocessors
Verilog
Logic Design
Eda
Ic
High Performance Computing
Embedded Systems
Arm
Rtl Design
Static Timing Analysis
System Architecture
Debugging
Perl
Algorithms
Computer Architecture
Architecture
Timing Closure
Physical Design
Interests:
Semiconductors
Mobile
Clean Technology
Health Care
Internet of Things
Consumer Internet
Sameer Halepete Photo 2

Sameer Halepete

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Us Patents

  • Delayed Bitline Leakage Compensation Circuit For Memory Devices

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  • US Patent:
    7085184, Aug 1, 2006
  • Filed:
    Sep 27, 2004
  • Appl. No.:
    10/951825
  • Inventors:
    Steven T. Walther - Mountain View CA, US
    Scott B. Kuusinen - Sunnyvale CA, US
    Sameer D. Halepete - San Jose CA, US
  • Assignee:
    nVidia Corporation - Santa Clara CA
  • International Classification:
    G11C 7/00
    G11C 7/10
  • US Classification:
    365203, 365204, 365207, 36518908
  • Abstract:
    A delayed bitline leakage compensation circuit for memory devices is disclosed. The delayed bitline leakage compensation circuit includes a bitline leakage model circuit for modeling discharge of a bitline by leakage current in a read operation. It further has a delayed charge signal generator for generating a delayed charge signal in response to the bitline leakage model circuit discharging to approximately a discharge threshold. The delayed charge signal generator is deactivated if the bitline is discharged by a selected memory cell. Moreover, the delayed bitline leakage compensation circuit includes a delayed charge circuit for charging the bitline in response to the delayed charge signal.

  • Adaptive Power Control

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  • US Patent:
    7100061, Aug 29, 2006
  • Filed:
    Jan 18, 2000
  • Appl. No.:
    09/484516
  • Inventors:
    Sameer Halepete - San Jose CA, US
    H. Peter Anvin - San Jose CA, US
    Zongjian Chen - Palo Alto CA, US
    Godfrey P. D'Souza - San Jose CA, US
    Marc Fleischmann - Menlo Park CA, US
    Keith Klayman - Sunnyvale CA, US
    Thomas Lawrence - Mountain View CA, US
    Andrew Read - Sunnyvale CA, US
  • Assignee:
    Transmeta Corporation - Santa Clara CA
  • International Classification:
    G06F 1/30
  • US Classification:
    713322
  • Abstract:
    A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.

  • Saving Power When In Or Transitioning To A Static Mode Of A Processor

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  • US Patent:
    7260731, Aug 21, 2007
  • Filed:
    Oct 23, 2000
  • Appl. No.:
    09/694433
  • Inventors:
    Andrew Read - Sunnyvale CA, US
    Sameer Halepete - San Jose CA, US
    Keith Klayman - Sunnyvale CA, US
  • Assignee:
    Transmeta Corporation - Santa Clara CA
  • International Classification:
    G06F 1/32
  • US Classification:
    713320, 713300
  • Abstract:
    A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.

  • Executing An Simd Instruction Requiring P Operations On An Execution Unit That Performs Q Operations At A Time (Q<P)

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  • US Patent:
    7484076, Jan 27, 2009
  • Filed:
    Sep 18, 2006
  • Appl. No.:
    11/532853
  • Inventors:
    Stuart F. Oberman - Sunnyvale CA, US
    Ming Y. Siu - Santa Clara CA, US
    Sameer D. Halepete - San Jose CA, US
  • Assignee:
    Nvidia Corporation - Santa Clara CA
  • International Classification:
    G06F 15/80
  • US Classification:
    712203, 712 22
  • Abstract:
    Methods, apparatuses, and systems are presented for performing instructions using multiple execution units in a graphics processing unit involving issuing an instruction for P executions of the instruction wherein each execution uses different data, P being a positive integer, the instruction being issued based on a first clock having a first clock rate, operating Q execution units to achieve the P executions of the instruction, Q being a positive integer less than P and greater than one, each of the execution units being operated based on a second clock having a second clock rate higher than the first clock rate of the first clock, and wherein the second clock rate of the second clock is equal to the first clock rate of the first clock multiplied by the ratio P/Q.

  • Adaptive Power Control

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  • US Patent:
    7596708, Sep 29, 2009
  • Filed:
    Apr 25, 2006
  • Appl. No.:
    11/411309
  • Inventors:
    Sameer Halepete - San Jose CA, US
    H. Peter Anvin - San Jose CA, US
    Zongjian Chen - Palo Alto CA, US
    Godfrey P. D'Souza - San Jose CA, US
    Marc Fleischmann - Menlo Park CA, US
    Keith Klayman - Sunnyvale CA, US
    Thomas Lawrence - Mountain View CA, US
    Andrew Read - Sunnyvale CA, US
  • International Classification:
    G06F 1/30
  • US Classification:
    713322
  • Abstract:
    A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.

  • Transitioning To And From A Sleep State Of A Processor

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  • US Patent:
    7870404, Jan 11, 2011
  • Filed:
    Aug 21, 2007
  • Appl. No.:
    11/894991
  • Inventors:
    Andrew Read - Sunnyvale CA, US
    Sameer Halepete - San Jose CA, US
    Keith Klayman - Sunnyvale CA, US
  • International Classification:
    G06F 1/32
  • US Classification:
    713320, 713323
  • Abstract:
    A method for reducing power utilized by a processor including determining that a processor is transitioning from a computer mode to a mode in which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.

  • Adaptive Power Control

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  • US Patent:
    8566627, Oct 22, 2013
  • Filed:
    Jul 14, 2009
  • Appl. No.:
    12/502685
  • Inventors:
    Sameer Halepete - San Jose CA, US
    H. Peter Anvin - San Jose CA, US
    Zongjian Chen - Palo Alto CA, US
    Godfrey P. D'Souza - San Jose CA, US
    Marc Fleischmann - Menlo Park CA, US
    Keith Klayman - Sunnyvale CA, US
    Thomas Lawrence - Mountain View CA, US
    Andrew Read - Sunnyvale CA, US
  • International Classification:
    G06F 1/00
    H03L 7/00
  • US Classification:
    713322, 331 17
  • Abstract:
    A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.

  • Saving Power When In Or Transitioning To A Static Mode Of A Processor

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  • US Patent:
    20110107131, May 5, 2011
  • Filed:
    Jan 10, 2011
  • Appl. No.:
    12/987423
  • Inventors:
    Andrew Read - Sunnyvale CA, US
    Sameer Halepete - San Jose CA, US
    Keith Klayman - Sunnyvale CA, US
  • International Classification:
    G06F 1/32
  • US Classification:
    713323
  • Abstract:
    A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.

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Sameer Halepete

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Friends:
Kristen Martin, Neeta Dodwad, Roshan Bharat, Anita Deshpande, Mrityunjay Dodwad
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