Sameer P Pendharkar

US Patent:

6395593, May 28, 2002

Filed:

Apr 17, 2000

Appl. No.:

09/550746

Inventors:

Sameer Pendharkar - Plano TX
Taylor R. Efland - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218238

US Classification:

438207, 438355

Abstract:

A method of minimizing parasitics in an MOS device caused by the formation of a bipolar transistor within the MOS devices and the device, primarily for a polyphase bridge circuit. For the low side device, a substrate of a first conductivity type is provided having a first buried layer of opposite conductivity type thereon. A second buried layer of the first conductivity type is formed over the first buried layer and a further layer of the first conductivity type is formed over the second buried layer. A sinker extending through the further layer to the first buried layer is formed to isolate the second buried layer and the further layer from the substrate. Formation of an MOS device in the further layer including source, drain and gate regions is completed and the sinker is connected to a source terminal of the device. The second buried layer is formed either by coimplanting a p-type dopant and an n-type dopant with one of the dopant having a higher diffusion rate than the other or by implanting and diffusing one of the two dopants first to form one layer and then implanting and diffusing the other dopant to form the second layer. The preferred dopants are boron as the p-type dopant and antimony as the n-type dopant.

US Patent:

6424005, Jul 23, 2002

Filed:

Dec 3, 1998

Appl. No.:

09/205657

Inventors:

Chin-Yu Tsai - HsinChu Hsien, TW
Taylor R. Efland - Richardson TX
Sameer Pendharkar - Richardson TX
John P. Erdeljac - Plano TX
Jozef Mitros - Richardson TX
Jeffrey P. Smith - Plano TX
Louis N. Hutter - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 31113

US Classification:

257335, 257283, 257336, 257344, 257345

Abstract:

An LDMOS device ( ) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells ( ). The Dwell ( ) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region ( ), which permits the n-type region of the Dwell to diffuse under the gate region ( ) an sufficient distance to eliminate misalignment effects.

US Patent:

6441431, Aug 27, 2002

Filed:

Dec 3, 1999

Appl. No.:

09/454934

Inventors:

Taylor Efland - Richardson TX
Chin-Yu Tsai - Plano TX
Sameer Pendharkar - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2976

US Classification:

257335, 257336, 257339

Abstract:

An embodiment of the instant invention is a transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region (well of FIG. ) formed in the semiconductor substrate (layer of FIG. ), the well region of a second conductivity type opposite that of the first conductivity type; a source region (source region of FIG. ) formed in the well region in the semiconductor substrate, the source region of the second conductivity type; a drain region (drain of FIG. ) formed in the semiconductor substrate and spaced away from the source region by a channel region (given by length L +L ), the drain region of the second conductivity type; a conductive gate electrode (layer of FIG. ) disposed over the semiconductor substrate and over the channel region; a gate insulating layer (layer of FIG. ) disposed between the conductive gate electrode and the semiconductor substrate and having a length, the gate insulating layer comprising: a first portion of the gate insulating layer which has a first length (L ) and a first thickness; a second portion of the gate insulating layer which has a second length (L ) and a second thickness which is substantially thicker than the first thickness, the sum of the first length and the second length equalling the length of the gate insulating layer; and wherein the first portion of the gate insulating layer being situated proximate to the source region and spaced away from the drain region by the second portion of the gate insulating layer; and wherein the well region having a dopant concentration less than that of the source region and the drain region, the well region extends at least from source region towards the drain region so as to completely underlie the first portion of the gate insulating layer and to underlie at least the second portion of the gate insulating layer.

US Patent:

6468837, Oct 22, 2002

Filed:

Aug 1, 2000

Appl. No.:

09/630594

Inventors:

Sameer P. Pendharkar - Plano TX
Taylor R. Efland - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21332

US Classification:

438140, 438151, 438286, 257328, 257336, 257339, 257342, 257409

Abstract:

A semiconductor device ( ) comprises a reduced surface field (RESURF) implant ( ). A field oxide layer ( ), having a length, is formed over the RESURF implant ( ). A field plate ( ) extends from a near-side of the field oxide layer ( ) and over at least one-half of the length of the field oxide layer ( ).

US Patent:

6624481, Sep 23, 2003

Filed:

Apr 4, 2003

Appl. No.:

10/407037

Inventors:

Sameer P. Pendharkar - Richardson TX
Philip L. Hower - Concord MA
Robert Steinhoff - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2362

US Classification:

257355, 257362, 257577

Abstract:

An ESD robust bipolar transistor ( ) that includes first and second bipolar elements ( ), wherein a first trigger voltage of the first bipolar element ( ) is proximate a second sustaining voltage of the second bipolar element ( ). The first and second bipolar elements ( ) include first and second bases ( ), emitters ( ) and collectors ( ), respectively. The first and second bases ( ) are coupled and the first and second collectors ( ) are coupled. The ESD robust bipolar transistor ( ) also includes an emitter resistor ( ) and a base resistor ( ), wherein the emitter resistor ( ) couples the first and second emitters ( ) and the base resistor ( ) couples the second emitter ( ) and the first and second bases ( ).

US Patent:

6670685, Dec 30, 2003

Filed:

May 24, 2002

Appl. No.:

10/155543

Inventors:

Sameer P. Pendharkar - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 31119

US Classification:

257409, 257470, 257339, 257605

Abstract:

A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide layer disposed outwardly from the drain region of the semiconductor substrate. The semiconductor device also includes a floating ring structure disposed inwardly from at least a portion of the field oxide layer. In one particular embodiment, a device parameter degradation associated with the semiconductor device comprises one (1) percent or less after approximately five hundred (500) seconds of accelerated lifetime operation.

US Patent:

6797547, Sep 28, 2004

Filed:

Oct 3, 2003

Appl. No.:

10/679220

Inventors:

Sheldon D. Haynie - Amherst NH
Steven L. Merchant - Bedford NH
Sameer P. Pendharkar - Richardson TX
Vladimir Bolkhovsky - Framingham MA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2100

US Classification:

438149, 438479, 438517, 438310, 438311, 438412, 438282, 257347, 257349, 257507

Abstract:

A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post. The process can be used with conventional bulk silicon wafers and processes, and the blade devices can be integrated with conventional planar devices formed on other areas of the wafer.

US Patent:

6800917, Oct 5, 2004

Filed:

Dec 17, 2002

Appl. No.:

10/321423

Inventors:

Sheldon D. Haynie - Amherst NH
Steven L. Merchant - Bedford NH
Sameer P. Pendharkar - Richardson TX
Vladimir Bolkhovsky - Framingham MA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2176

US Classification:

257506, 257524, 257E21553, 257E21564

Abstract:

A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post. The process can be used with conventional bulk silicon wafers and processes, and the blade devices can be integrated with conventional planar devices formed on other areas of the wafer.