Sami S Issa

US Patent:

6480424, Nov 12, 2002

Filed:

Oct 12, 2001

Appl. No.:

09/976236

Inventors:

Sami Issa - Phoenix AZ

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 1604

US Classification:

36518902, 365205, 365190

Abstract:

The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. The respective local sense amplifiers for the non-selected global bit lines just read and refresh the respective memory cells resulting in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers). In one embodiment, eight global bit lines are shared by one global sense amplifier and are multiplexed. Only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global bit line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development. Thus, the respective activated sense amplifiers amplify only the cell data which reassembles a read and refresh operation.

US Patent:

6574136, Jun 3, 2003

Filed:

Nov 20, 2001

Appl. No.:

09/989595

Inventors:

Cyrus Afghahi - Mission Viejo CA
Sami Issa - Phoenix AZ
Zeynep Toros - Irvine CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 11401

US Classification:

365149, 365 63, 365 72

Abstract:

A random access memory cell ( ) includes a first conductor line ( ) and a second conductor line ( ). A native device ( ) is arranged to store charge. A high voltage threshold transistor ( ) couples the native device to the first and second conductors.

US Patent:

6600677, Jul 29, 2003

Filed:

Oct 19, 2001

Appl. No.:

10/037599

Inventors:

Cyrus Afghahi - Mission Viejo CA
Sami Issa - Phoenix AZ

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 1134

US Classification:

365187, 365222, 36518904

Abstract:

A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.

US Patent:

6646954, Nov 11, 2003

Filed:

Mar 19, 2002

Appl. No.:

10/100757

Inventors:

Gil I. Winograd - Aliso Viejo CA
Esin Terzioglu - Aliso Viejo CA
Ali Anvar - Irvine CA
Sami Issa - Phoenix AZ

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 800

US Classification:

365233, 36523003, 365 63

Abstract:

The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.

US Patent:

6650563, Nov 18, 2003

Filed:

Apr 23, 2002

Appl. No.:

10/128328

Inventors:

Sami Issa - Phoenix AZ

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 1124

US Classification:

365149, 36518526

Abstract:

A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.

US Patent:

6650572, Nov 18, 2003

Filed:

Aug 21, 2002

Appl. No.:

10/224841

Inventors:

Sami Issa - Phoenix AZ

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 1604

US Classification:

36518902, 365205, 365190

Abstract:

The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. As a result, the respective local sense amplifiers for the non-selected global bit lines will just read and refresh the respective memory cells. This new approach results in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers). In one embodiment, eight global bit lines are shared by one global sense amplifier and multiplexed to achieve the advantages of the present invention. Due to an analog global multiplexing scheme used by the present invention, only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global bit line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development. The global bit line pairs with no voltage development generate zero voltage development on the local bit lines and the respective activated sense amplifiers amplify only the cell data which reassembles a read and refresh operation.

US Patent:

6653876, Nov 25, 2003

Filed:

Apr 23, 2002

Appl. No.:

10/128325

Inventors:

Sami Issa - Phoenix AZ
Morteza (Cyrus) Afghahi - Mission Viejo CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 700

US Classification:

327158, 327153

Abstract:

A method and apparatus are disclosed for efficiently doubling a first frequency of a first clock signal. A second clock signal at a second frequency is generated by dividing the first frequency of the first clock signal by two, such that the second frequency is half of the first frequency and a duty cycle of the second clock signal is 50%. Also, a set of phase-delayed clock signals is generated in response to the second clock signal such that the set of phase-delayed clock signals are delayed in phase with respect to the second clock signal. Further, the set of phase-delayed clock signals is combined to generate a third clock signal at a third frequency, such that the third frequency is twice that of the first frequency and a duty cycle of the third clock signal is 50%.

US Patent:

6678198, Jan 13, 2004

Filed:

Aug 3, 2001

Appl. No.:

09/921606

Inventors:

Sami Issa - Phoenix AZ
Morteza Cyrus Afghahi - Mission Viejo CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 714

US Classification:

365207, 365210, 365187, 36518907

Abstract:

Present invention describes an efficient implementation of differential sensing in single ended DRAM arrays. According to one embodiment of the present invention, a respective local sense amplifier compares the accessed memory cell data with a dummy cell data in the opposite or adjacent block of the accessed block that is connected to a respective local bit line in the opposite block, amplifies the result of the comparison and puts the data on a global bit line. In one embodiment, the invention is process and temperature invariant using reference method and means for canceling cross coupling between read lines and write lines.