Samuel J Fuller

US Patent:

20210050417, Feb 18, 2021

Filed:

Jan 29, 2019

Appl. No.:

16/966893

Inventors:

- Cambridge MA, US
Tathagata SRIMANI - Cambridge MA, US
Samuel FULLER - Cambridge MA, US
Yosi STEIN - Norwood MA, US
Denis MURPHY - Norwood MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H01L 29/06
H01L 51/00
H01L 51/05

Abstract:

A back-gate carbon nanotube field effect transistor (CNFETs) provides: (1) reduced parasitic capacitance, which decreases the energy-delay product (EDP) thus improving the energy efficiency of digital systems (e.g., very-large-scale integrated circuits) and (2) scaling of transistors to smaller technology nodes (e.g., sub-3 nm nodes). An exemplary back-gate CNFET includes a channel. A source and a drain are disposed on a first side of the channel. A gate is disposed on a second side of the channel opposite to the first side. In this manner, the contacted gate pitch (CGP) of the back-gate CNFET may be scaled down without scaling the physical gate length (L) or contact length (L). The gate may also overlap with the source and/or the drain in this architecture. In one example, an exemplary CNFET was demonstrated to have a CGP less than 30 nm and 1.6× improvement to EDP compared to top-gate CNFETs.