Samuel W Ho

US Patent:

6411651, Jun 25, 2002

Filed:

Jun 26, 1998

Appl. No.:

09/105059

Inventors:

Robert C. Rose - Hudson MA
Matthew J. Adiletta - Worcester MA
Samuel W. Ho - Marlboro MA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

H04N 712

US Classification:

37524013, 382234

Abstract:

A method and system for compressing video data in a computer has video processing that is distributed between preprocessing hardware in a video capture/controller card and a central processing unit of the computer. Frames of video data are passed to a motion estimation unit of the preprocessing hardware. This unit generates motion information describing inter-frame changes in the video data. Next, motion-compensated temporal filtering is performed on the frames of video data using the motion information. A video frame processing unit of the controller card, used for processing video data to the monitor, is reused for the temporal filtering of the input video data. Finally, the temporally-filtered video data is passed to the central processing unit, which performs inter-frame and/or intra-frame compression with reference to the motion information. In this way, motion-compensated temporal filtering is performed, thus removing the associated noise without adding to the CPUs processing burden, but the costs associated with dedicated compression hardware are avoided by relying on the video capture capabilities in the video controller card.

US Patent:

6760478, Jul 6, 2004

Filed:

Jul 10, 2000

Appl. No.:

09/613359

Inventors:

Matthew James Adiletta - Worcester MA
King-Wai Chow - Marlboro MA
Samuel William Ho - Marlborough MA
Robert Clint Rose - Hudson MA
William Ralph Wheeler - Southborough MA
Duane E. Galbi - Marlborough MA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06K 936

US Classification:

382236, 382239, 37524002, 37524013, 37524016

Abstract:

An apparatus and method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipelining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and therefore provide a more appealing output image.

US Patent:

6980595, Dec 27, 2005

Filed:

Jun 24, 2002

Appl. No.:

10/179659

Inventors:

Robert C. Rose - Hudson MA, US
Matthew J. Adiletta - Worcester MA, US
Samuel W. Ho - Marlboro MA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H04N007/12
H04N007/15

US Classification:

37524013

Abstract:

A method and system for compressing video data in a computer has video processing that is distributed between preprocessing hardware in a video capture/controller card and a central processing unit of the computer. Frames of video data are passed to a motion estimation unit of the preprocessing hardware. This unit generates motion information describing inter-frame changes in the video data. Next, motion-compensated temporal filtering is performed on the frames of video data using the motion information. A video frame processing unit of the controller card, used for processing video data to the monitor, is reused for the temporal filtering of the input video data. Finally, the temporally-filtered video data is passed to the central processing unit, which performs inter-frame and/or intra-frame compression with reference to the motion information. In this way, motion-compensated temporal filtering is performed, thus removing the associated noise without adding to the CPU's processing burden, but the costs associated with dedicated compression hardware are avoided by relying on the video capture capabilities in the video controller card.

US Patent:

7006698, Feb 28, 2006

Filed:

Nov 25, 2003

Appl. No.:

10/721947

Inventors:

Matthew James Adiletta - Worcester MA, US
King-Wai Chow - Marlboro MA, US
Samuel William Ho - Marlborough MA, US
Robert Clint Rose - Hudson MA, US
William Ralph Wheeler - Southborough MA, US
Subramania Iyer Sudharsanan - San Jose CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06K 9/36
H04N 7/12

US Classification:

382236, 382239, 37524012, 37524002

Abstract:

An apparatus and method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantification values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipe lining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and therefore provide a more appealing output image.

US Patent:

20050276329, Dec 15, 2005

Filed:

Aug 15, 2005

Appl. No.:

11/204939

Inventors:

Matthew Adiletta - Worcester MA, US
Samuel Ho - Marlborough MA, US
Subramania Sudharsanan - San Jose CA, US

International Classification:

H04N007/12

US Classification:

375240160, 375240240

Abstract:

An apparatus and method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipelining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and therefore provide a more appealing output image.

US Patent:

20090131310, May 21, 2009

Filed:

May 13, 2005

Appl. No.:

11/596273

Inventors:

Samuel B. Ho - San Diego CA, US
Laurie L. Shekels - Mound MN, US

International Classification:

A61K 38/17
C07H 21/04
C07K 14/435
C12N 1/21
C12N 1/19
C12N 5/10
C12N 15/63

US Classification:

514 12, 536 235, 4353201, 530324, 530350, 435325, 435348, 4352523, 4352542

Abstract:

The invention provides for a mucin3 polypeptide, a polypeptide including a mucin3 EGF-like domain, and nucleic acids encoding such polypeptides. The invention also provides for methods of treating an individual that has or is at risk of developing a disease or condition of the alimentary canal using such polypeptides or nucleic acids.

US Patent:

20120021987, Jan 26, 2012

Filed:

Feb 7, 2011

Appl. No.:

13/022307

Inventors:

Samuel B. Ho - La Jolla CA, US
Laurie L. Shekels - Mound MN, US

Assignee:

MuciMed, Inc. - Kalamazoo MI

International Classification:

A61K 38/17
A61P 35/00
A61P 17/02
A61P 27/02
C07K 14/47
A61P 29/00
A61P 15/02
A61P 15/00
A61P 11/00
A61P 1/02
A61P 17/06
A61P 1/04
A61P 1/00

US Classification:

514 132, 514 193, 514 209, 514 186, 514 208, 530395

Abstract:

The invention provides for a mucin3 polypeptide, a polypeptide including a mucin3 EGFlike domain, and nucleic acids encoding such polypeptides. The invention also provides for methods of treating an individual that has or is at risk of developing a disease or condition of the alimentary canal using such polypeptides or nucleic acids.

US Patent:

59681535, Oct 19, 1999

Filed:

Oct 13, 1998

Appl. No.:

9/170812

Inventors:

William R. Wheeler - Southboro MA
Matthew James Adiletta - Worcester MA
Samuel Ho - Marlboro MA
Debra Bernstein - Sudbury MA
Gilbert M. Wolrich - Framingham MA

Assignee:

Digital Equipment Corporation - Houston TX

International Classification:

G06F 1300

US Classification:

710110

Abstract:

A method and apparatus for maximizing the performance of DMA transfers over a PCI. TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read Semaphore functionality, a method for servicing of DMA transfers during FMU latency periods, Valid bit functionality, high and low water thresholds, and re-usable page tables.