Samuel L Martin

Address:

2237 NW Edgewood Pl, Portland, OR 97229

VIN:

WMWMF33527TT57078

Make:

MINI

Model:

COOPER

Year:

2007

US Patent:

7892610, Feb 22, 2011

Filed:

May 2, 2008

Appl. No.:

12/114446

Inventors:

J. Wallace Parce - Palo Alto CA, US
James M. Hamilton - Sunnyvale CA, US
Samuel Martin - Cupertino CA, US
Erik Freer - Camptell CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

B05D 1/04

US Classification:

427475, 427458, 427466

Abstract:

Methods and systems for applying nanowires and electrical devices to surfaces are described. In a first aspect, at least one nanowire is provided proximate to an electrode pair. An electric field is generated by electrodes of the electrode pair to associate the at least one nanowire with the electrodes. The electrode pair is aligned with a region of the destination surface. The at least one nanowire is deposited from the electrode pair to the region. In another aspect, a plurality of electrical devices is provided proximate to an electrode pair. An electric field is generated by electrodes of the electrode pair to associate an electrical device of the plurality of electrical devices with the electrodes. The electrode pair is aligned with a region of the destination surface. The electrical device is deposited from the electrode pair to the region.

US Patent:

7968474, Jun 28, 2011

Filed:

Nov 9, 2007

Appl. No.:

11/979949

Inventors:

Samuel Martin - Cupertino CA, US
Xiangfeng Duan - Mountain View CA, US
Katsumasa Fujii - Yamatokoriyama, JP
James M. Hamilton - Sunnyvale CA, US
Hiroshi Iwata - Nara, JP
Francisco Leon - Palo Alto CA, US
Jeffrey Miller - Los Altos Hills CA, US
Tetsu Negishi - Sunnyvale CA, US
Hiroshi Ohki - Tokyo, JP
J. Wallace Parce - Palo Alto CA, US
Paul John Schuele - Washougal WA, US
Akihide Shibata - Santa Clara CA, US
David P. Stumbo - Belmont CA, US
Yasunobu Okada - Gifu, JP

Assignee:

Nanosys, Inc. - Mountain View CA
Sharp Kabushiki Kaisha - Osaka

International Classification:

H01L 21/71

US Classification:

438800, 257E21536, 977883

Abstract:

The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e. g. , an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

US Patent:

8252164, Aug 28, 2012

Filed:

May 23, 2011

Appl. No.:

13/113680

Inventors:

Samuel Martin - Cupertino CA, US
Xiangfeng Duan - Mountain View CA, US
Katsumasa Fujii - Yamatokoriyama, JP
James M. Hamilton - Sunnyvale CA, US
Hiroshi Iwata - Nara, JP
Francisco Leon - Palo Alto CA, US
Jeffrey Miller - Los Altos Hills CA, US
Tetsu Negishi - Sunnyvale CA, US
Hiroshi Ohki - Tokyo, JP
J. Wallace Parce - Palo Alto CA, US
Paul John Schuele - Washougal WA, US
Akihide Shibata - Santa Clara CA, US
David P. Stumbo - Belmont CA, US
Yasunobu Okada - Gifu, JP

Assignee:

Nanosys, Inc. - Palo Alto CA
Sharp Kabushiki Kaisha - Osaka

International Classification:

C25D 13/02

US Classification:

204622, 204477, 977883

Abstract:

The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e. g. , an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

US Patent:

20110165337, Jul 7, 2011

Filed:

Jan 19, 2011

Appl. No.:

13/009675

Inventors:

J. Wallace Parce - Palo Alto CA, US
James M. Hamilton - Sunnyvale CA, US
Samuel Martin - Cupertino CA, US
Erik Freer - Campbell CA, US

Assignee:

NANOSYS, INC. - Palo Alto CA

International Classification:

B05D 1/04
B05B 5/025

US Classification:

427466, 118621, 427475

Abstract:

Methods and systems for applying nanowires and electrical devices to surfaces are described. In a first aspect, at least one nanowire is provided proximate to an electrode pair. An electric field is generated by electrodes of the electrode pair to associate the at least one nanowire with the electrodes. The electrode pair is aligned with a region of the destination surface. The at least one nanowire is deposited from the electrode pair to the region. In another aspect, a plurality of electrical devices is provided proximate to an electrode pair. An electric field is generated by electrodes of the electrode pair to associate an electrical device of the plurality of electrical devices with the electrodes. The electrode pair is aligned with a region of the destination surface. The electrical device is deposited from the electrode pair to the region.

US Patent:

59630973, Oct 5, 1999

Filed:

Jan 27, 1998

Appl. No.:

9/014325

Inventors:

Alexander Viktorovich Garachtchenko - Mountain View CA
Samuel Suresh Martin - Gillette NJ

International Classification:

H03F 304
H03F 316
H03F 345

US Classification:

330310

Abstract:

A low-noise amplifier is disclosed that is capable of amplifying a signal with high gain (e. g. , >60 dB) and low noise (e. g. , 10. sup. 6. OMEGA. ), high common mode rejection and high immunity to external noise sources. An illustrative embodiment of the present invention comprises: a first field-effect transistor having a first lead, a second lead and a third lead; a second field-effect transistor having a first lead, a second lead and a third lead, wherein the first lead of the first field-effect transistor is electrically connected to the first lead of the second field-effect transistor, the second lead of the first field-effect transistor is electrically connected to the second lead of the second field-effect transistor, and the third lead of the first field-effect transistor is electrically connected to the third lead of the second field-effect transistor; and a first bipolar junction transistor having a first lead, a second lead and a third lead, wherein the first lead of the first bipolar junction transistor is electrically connected to the first lead of the first field-effect transistor.