Samuel K Tam

US Patent:

8385073, Feb 26, 2013

Filed:

Jul 6, 2010

Appl. No.:

12/831033

Inventors:

Samuel Tam - Daly City CA, US
Younes Shabany - San Jose CA, US

Assignee:

Flextronics AP, LLC - Broomfield CO

International Classification:

H05K 7/20
H05K 3/36

US Classification:

361721, 36167954, 361697, 361702, 361709

Abstract:

A folded system-in-package (SiP) assembly is provided for minimizing the footprint of two corresponding circuit board modules in a handheld electronic device. The assembly includes top and bottom circuit board modules that are electrically interconnected through a flex circuit. Either a plate or wrapped heat spreader may be thermally coupled to the top circuit board module to conduct heat from the heat-generating components mounted to the top circuit board module and to a case of the electronic device.

US Patent:

8430579, Apr 30, 2013

Filed:

Jan 11, 2011

Appl. No.:

12/930606

Inventors:

Samuel Waising Tam - Daly City CA, US
Tai Wai (David) Pun - Hong Kong, CN
Tak Shing (Dick) Pang - Hong Kong, CN

Assignee:

Flextronics AP, LLC - Broomfield CO

International Classification:

G03B 17/00

US Classification:

396529, 396542

Abstract:

A novel design and method for manufacturing camera modules is disclosed. The camera module includes a flexible circuit substrate, an image capture device flip-chip mounted to the bottom surface of the flexible circuit substrate, a housing mounted over the top surface of the flexible circuit substrate, and a lens unit coupled to the housing. In an example embodiment, the camera module includes a stiffener formed directly over a plurality of electrical components mounted on the top surface of the flexible circuit substrate. In another example embodiment, the bottom surface of the flexible circuit substrate defines a recessed portion whereon the image capture device is flip-chip mounted. A disclosed method for manufacturing camera modules includes providing a flexible circuit tape having a plurality of discrete circuit regions, providing a plurality of image capture devices, flip-chip mounting each image capture device on an associate one of the discrete circuit regions, providing a plurality of housings, and mounting each housing on an associate one of the discrete circuit regions.

US Patent:

8642387, Feb 4, 2014

Filed:

Nov 1, 2011

Appl. No.:

13/286366

Inventors:

Samuel Tam - Daly City CA, US
Bryan Lee Sik Pong - Bukit Raja, MY
Dick Pang - Tsuen Wan, HK

Assignee:

Flextronics AP, LLC - Broomfield CO

International Classification:

H01L 21/00
H01L 23/02

US Classification:

438113, 438126, 438127, 257686, 257788, 257E23069, 257E21502

Abstract:

Described herein is a stacked package using laser direct structuring. The stacked package includes a die attached to a substrate. The die is encapsulated with a laser direct structuring mold material. The laser direct structuring mold material is laser activated to form circuit traces on the top and side surfaces of the laser direct structuring mold material. The circuit traces then undergo metallization. A package is then attached to the metalized circuit traces and is electrically connected to the substrate via the metalized circuit traces.

US Patent:

20020121707, Sep 5, 2002

Filed:

Feb 25, 2002

Appl. No.:

10/084787

Inventors:

Rajendra Pendse - Fremont CA, US
Samuel Tam - Daly City CA, US

Assignee:

ChipPAC, Inc. - Fremont CA

International Classification:

H01L021/44

US Classification:

257/778000, 438/108000

Abstract:

A chip package achieves miniaturization and excellent high-speed operation by employing flip chip interconnection between the die and the package substrate, and mounting the chip on the same side of the package substrate as the solder balls for the second level interconnection to the printed circuit board. Also, two-die packages have a first die attached to the same surface as the second level interconnect structures and connected using flip chip interconnection, and a second die connected to the opposite surface of the substrate and interconnected either by wire bonding or by flip chip interconnection.

US Patent:

20020151189, Oct 17, 2002

Filed:

Feb 22, 2002

Appl. No.:

10/081491

Inventors:

Rajendra Pendse - Fremont CA, US
Nazir Ahmad - San Jose CA, US
Andrea Chen - San Jose CA, US
Kyung-Moon Kim - Ichon-si, KR
Young-Do Kweon - Pleasanton CA, US
Samuel Tam - Daly City CA, US

Assignee:

ChipPAC, Inc. - Fremont CA

International Classification:

H01L023/48
H01L021/56

US Classification:

438/778000, 438/126000, 438/108000, 438/613000, 257/737000, 438/787000

Abstract:

A flip chip package is formed by a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material. Accordingly the connections are capable of carrying very high current, and display good long-term reliability as compared to ACA or ICA particulate interconnects. Moreover the solid-state bond technique does not entail a melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries, typically as low as 70 micrometers pitch. Also, the space between the surface of the integrated circuit chip and the subjacent surface of the package substrate is filled with a patterned adhesive structure, which consists of one or more adhesive materials that are deployed in a specified pattern in relation to the positions of the second level interconnections between the package and the printed circuit board. According to this aspect of the invention, the coefficient of thermal expansion and the compliancy of the package structure in the regions overlying the second level connections can be tailored to reduce potentially damaging propagation of stress generated in the second level connections on the package to features on the integrated circuit chip, and thereby extending the long-term reliability of the package and of the interconnects.

US Patent:

20040222440, Nov 11, 2004

Filed:

May 4, 2004

Appl. No.:

10/838639

Inventors:

Rajendra Pendse - Fremont CA, US
Nazir Ahmad - San Jose CA, US
Andrea Chen - San Jose CA, US
Kyung-Moon Kim - Ichon-si, KR
Young Kweon - Cupertino CA, US
Samuel Tam - Daly City CA, US

Assignee:

ChipPAC, Inc - Fremont CA

International Classification:

H01L027/10

US Classification:

257/202000

Abstract:

A flip chip package is formed by a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material. Accordingly the connections are capable of carrying very high current, and display good long-term reliability as compared to ACA or ICA particulate interconnects. Moreover the solid-state bond technique does not entail a melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries, typically as low as micrometers pitch. Also, the space between the surface of the integrated circuit chip and the subjacent surface of the package substrate is filled with a patterned adhesive structure, which consists of one or more adhesive materials that are deployed in a specified pattern relation to the positions of the second level interconnections between the package and the printed circuit board. According to this aspect of the invention, the coefficient of thermal expansion and the compliancy of the package structure in the regions overlying the second level connections can be tailored to reduce potentially damaging propagation of stress generated in the second level connections on the package to features on the integrated circuit chip, and thereby extending the long-term reliability of the package and of the interconnects.

US Patent:

20050056944, Mar 17, 2005

Filed:

Oct 7, 2004

Appl. No.:

10/960893

Inventors:

Rajendra Pendse - Fremont CA, US
Samuel Tam - Daly City CA, US

Assignee:

ChipPAC, Inc. - Fremont CA

International Classification:

H01L023/52

US Classification:

257778000, 257738000, 257780000

Abstract:

A chip package achieves miniaturization and excellent high-speed operation by employing flip chip interconnection between the die and the package substrate, and mounting the chip on the same side of the package substrate as the solder balls for the second level interconnection to the printed circuit board. Also, two-die packages have a first die attached to the same surface as the second level interconnect structures and connected using flip chip interconnection, and a second die connected to the opposite surface of the substrate and interconnected either by wire bonding or by flip chip interconnection.

US Patent:

20070236591, Oct 11, 2007

Filed:

Apr 11, 2006

Appl. No.:

11/402196

Inventors:

Samuel Tam - Daly City CA, US
Dongkai Shangguan - San Jose CA, US

International Classification:

H04N 5/335
H01S 4/00

US Classification:

348308000, 029832000, 348374000, 348340000, 029592100

Abstract:

A method for manufacturing camera modules including image capture devices with protective covers is disclosed. The method includes providing a unitary transparent substrate including a plurality of individual protective covers, providing a unitary component substrate including a plurality of individual component parts, bonding the unitary transparent substrate to the unitary component substrate, dividing the transparent substrate into a plurality of discrete protective covers, and separating the component parts from one another. According to one particular method, the component substrate is a semiconductor wafer having a plurality of integrated electronic image capture devices formed therein. According to another particular method, the component substrate is a circuit board having a plurality of individual device circuit boards formed therein.