Sandeep A Gupta

US Patent:

6362698, Mar 26, 2002

Filed:

Sep 29, 2000

Appl. No.:

09/675973

Inventors:

Sandeep K. Gupta - Mountain View CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03B 512

US Classification:

331117FE, 331 34, 331167, 331117 R, 331185, 330 98, 330310

Abstract:

A circuit for conditioning an input control voltage signal that is used to drive an LC tank oscillator in a phase locked loop (PLL). The conditioning circuit includes a two-stage amplifier including a first stage amplifier connected to a second stage comprising an active cascode circuit, a diode-connected transistor and a resistor tied to a reference voltage (e. g. ground). The first stage amplifier receives a control voltage input signal, which would typically be produced at the output of a loop filter in a PLL, and produces a conditioned control voltage output signal at its output, which is connected to the drain of the diode-connected transistor. The purpose of the amplifier is to lower the impedance of the conditioned output signal, which is then used to drive the LC tank oscillator, wherein the series resistor acts both to lower the impedance and to act as the degenerating resistor for the diode-connected transistor. In addition, a clamping circuit comprising a second active cascode structure is provided to clamp the conditioned control voltage output signal such that it is prevented from falling below a predetermined value.

US Patent:

6369620, Apr 9, 2002

Filed:

Sep 29, 2000

Appl. No.:

09/672953

Inventors:

Sandeep K. Gupta - Mountain View CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 300

US Classification:

327108, 327 66, 327101, 330288

Abstract:

A cross coupled output stage for a transmitter. It is desirable to have high impedance for a differential cascode output stage of an externally terminated transmitter in order to improve return loss. However, at high frequencies, parasitic capacitances cause shunts at the output nodes due to drain to bulk capacitances and negative feedback loops due to gate-to-drain capacitance. In order to counteract this, cross coupled capacitors are connected to the circuit to cause a positive feedback loop. This counteracts the reduction in impedance causing the impedance to remain high over all frequencies and to improve the return loss.

US Patent:

6529058, Mar 4, 2003

Filed:

Sep 21, 2001

Appl. No.:

09/956978

Inventors:

Sandeep Kumar Gupta - Mountain View CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03H 1126

US Classification:

327276

Abstract:

A circuit and method for obtaining a stable delay for a clock signal comprises a current source to generate a constant current having a first value; first and second current over capacitance (I/C) stages coupled to the current source and between a supply voltage and ground; and a capacitor, having a second value and coupled to a node formed by an output of the first I/C stage and an input of the second I/C stage. Application of a clock signal to an input of the first I/C stage produces an output at a logic gate coupled to an output of the second I/C stage. The output has a stable delay based on the first and second values. Additionally, the first and second values (i. e. , the value of the current or capacitance) can be changed to achieve a desired amount of the delay applied to the input clock signal.

US Patent:

6680650, Jan 20, 2004

Filed:

Aug 30, 2001

Appl. No.:

09/941694

Inventors:

Sandeep K. Gupta - Mountain View CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03F 316

US Classification:

330277, 330296, 327534

Abstract:

A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a MOSFET and applying this replicated voltage to the body terminal. In this manner, the effect of the body transconductance, at high frequencies, becomes a function of the ratio of the well-to-substrate capacitance of the MOSFET to the sum of the well-to-substrate capacitance and the source-to-body capacitance of the transistor. At high frequencies, the biasing scheme mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET by contributing a negative half plane zero to the transfer function of the feedback network, and reduces the power consumed by the gain boosting amplifier.

US Patent:

6720799, Apr 13, 2004

Filed:

Jul 25, 2001

Appl. No.:

09/911498

Inventors:

Sandeep K. Gupta - Mountain View CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 2702

US Classification:

327 92, 327558, 327337

Abstract:

The present invention relates to a replica network for linearizing switched capacitor circuits. A bridge circuit with a MOSFET resistor disposed in a resistor branch of the bridge circuit is provided. A noninverting terminal of an operational amplifier is connected to a first node of the bridge circuit and an inverting terminal of the operational amplifier is connected to a second node of the bridge circuit. The second node is separated from the first node by another node of the bridge circuit. An output of the operational amplifier is provided to a gate terminal of the MOSFET resistor and to the gate terminal of the MOSFET switch in a switched capacitor circuit, thereby controlling the resistance of the MOSFET switch so that it is independent of the signal voltage. In this manner, the replica network of the present invention linearizes the switched capacitor circuit. In this manner, the replica network of the present invention linearizes the switched capacitor circuit.

US Patent:

6750795, Jun 15, 2004

Filed:

Jan 14, 2002

Appl. No.:

10/043229

Inventors:

Sandeep K. Gupta - Aliso Viejo CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M 300

US Classification:

341143, 341118, 341120, 341139, 341144, 341155

Abstract:

Gain scaling of multistage, multi-bit delta sigma modulators for higher signal-to-noise ratios. In a multistage delta sigma modulator having a modulator stage with an integrator, a multi-bit quantizer, and a multi-bit digital-to-analog converter, the multi-bit quantizer is companded to cause a feedback signal, produced by the multi-bit digital-to-analog converter, to have a first gain, with respect to an integrated signal received by the multi-bit quantizer, set greater than one. A second gain, of the integrator, is reduced so that an overall gain of the modulator stage remains equal to one. A third gain, of a stability correction gain element connected to an input of the modulator stage, is increased so that a swing of the integrated signal remains within a dynamic range of an operational amplifier used to implement the integrator, and the multistage delta sigma modulator can realize the higher signal-to-noise ratio.

US Patent:

6795002, Sep 21, 2004

Filed:

Dec 23, 2002

Appl. No.:

10/326706

Inventors:

Sandeep K. Gupta - Aliso Viejo CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M 300

US Classification:

341143, 341155

Abstract:

An n-bit quantizer of a downstream modulator stage is configured to produce an n-bit quantized signal from an analog signal having a range. The n-bit quantizer divides the range into 2 subranges. A first subrange of the 2 subranges is bounded by a lowest value of the range, a second subrange of the 2 subranges is bounded by a highest value of the range, and at least one remaining subrange of the 2 subranges is positioned between the first and the second subranges. The first and the second subranges each measure greater than {1/[2(2 -1)]} of the total range. Each of the at least one remaining subrange measures less than [1/(2 -1)] of the total range. A first gain of an integrator of the downstream modulator stage is set so that the downstream modulator stage is stable. A second gain of a stability correction gain element of a coupling stage connected to the downstream modulator is set so that a swing of the analog signal remains within a dynamic range of the downstream modulator stage.

US Patent:

6809672, Oct 26, 2004

Filed:

Mar 24, 2003

Appl. No.:

10/394196

Inventors:

Sandeep K. Gupta - Aliso Viejo CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M 300

US Classification:

341143, 341172

Abstract:

In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock. This configuration: (1) eliminates poles from the transfer function that defines processing of a signal by the high order delta sigma modulator stage, (2) reduces the power consumed by the high order delta sigma modulator stage for a given settling time requirement, (3) facilitates reducing the size of the summing junction switches in the high order delta sigma modulator stage to decrease distortions due to charge injections, and (4) allows a reference signal voltage, which is coupled to a cross coupled feedback switched capacitor network in the integrators, to be set equal to one of two power supply voltages for the high order delta sigma modulator stage, thereby further reducing the power consumed by the delta sigma modulator.