Sandeep Gupta

US Patent:

6750795, Jun 15, 2004

Filed:

Jan 14, 2002

Appl. No.:

10/043229

Inventors:

Sandeep K. Gupta - Aliso Viejo CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M 300

US Classification:

341143, 341118, 341120, 341139, 341144, 341155

Abstract:

Gain scaling of multistage, multi-bit delta sigma modulators for higher signal-to-noise ratios. In a multistage delta sigma modulator having a modulator stage with an integrator, a multi-bit quantizer, and a multi-bit digital-to-analog converter, the multi-bit quantizer is companded to cause a feedback signal, produced by the multi-bit digital-to-analog converter, to have a first gain, with respect to an integrated signal received by the multi-bit quantizer, set greater than one. A second gain, of the integrator, is reduced so that an overall gain of the modulator stage remains equal to one. A third gain, of a stability correction gain element connected to an input of the modulator stage, is increased so that a swing of the integrated signal remains within a dynamic range of an operational amplifier used to implement the integrator, and the multistage delta sigma modulator can realize the higher signal-to-noise ratio.

US Patent:

6795002, Sep 21, 2004

Filed:

Dec 23, 2002

Appl. No.:

10/326706

Inventors:

Sandeep K. Gupta - Aliso Viejo CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M 300

US Classification:

341143, 341155

Abstract:

An n-bit quantizer of a downstream modulator stage is configured to produce an n-bit quantized signal from an analog signal having a range. The n-bit quantizer divides the range into 2 subranges. A first subrange of the 2 subranges is bounded by a lowest value of the range, a second subrange of the 2 subranges is bounded by a highest value of the range, and at least one remaining subrange of the 2 subranges is positioned between the first and the second subranges. The first and the second subranges each measure greater than {1/[2(2 -1)]} of the total range. Each of the at least one remaining subrange measures less than [1/(2 -1)] of the total range. A first gain of an integrator of the downstream modulator stage is set so that the downstream modulator stage is stable. A second gain of a stability correction gain element of a coupling stage connected to the downstream modulator is set so that a swing of the analog signal remains within a dynamic range of the downstream modulator stage.

US Patent:

6809672, Oct 26, 2004

Filed:

Mar 24, 2003

Appl. No.:

10/394196

Inventors:

Sandeep K. Gupta - Aliso Viejo CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M 300

US Classification:

341143, 341172

Abstract:

In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock. This configuration: (1) eliminates poles from the transfer function that defines processing of a signal by the high order delta sigma modulator stage, (2) reduces the power consumed by the high order delta sigma modulator stage for a given settling time requirement, (3) facilitates reducing the size of the summing junction switches in the high order delta sigma modulator stage to decrease distortions due to charge injections, and (4) allows a reference signal voltage, which is coupled to a cross coupled feedback switched capacitor network in the integrators, to be set equal to one of two power supply voltages for the high order delta sigma modulator stage, thereby further reducing the power consumed by the delta sigma modulator.

US Patent:

6856201, Feb 15, 2005

Filed:

Jul 22, 2004

Appl. No.:

10/896233

Inventors:

Sandeep K. Gupta - Aliso Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03F003/08

US Classification:

330308, 250214 A, 330297

Abstract:

A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a pluraty of power sources and a bias current portion having a pluraty of bias current devices. The system also includes an amplification portion having a plurality of amplifiers. A first group of the plurality of amplifiers is coupled to the power source portion and the bias current portion, such that feedback voltage is substantially eliminated to substantially eliminate oscillations in the amplification portion.

US Patent:

6882218, Apr 19, 2005

Filed:

Aug 26, 2002

Appl. No.:

10/227257

Inventors:

Sandeep K. Gupta - Aliso Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03F001/02

US Classification:

330 9, 330260, 327341, 327562

Abstract:

A system for receiving signals (e. g. , optical signals) includes an input device, an amplification device, and a feedback device. The amplification device receives a signal from the input device and includes a transimpedance portion. The transimpedance portion includes a first section having a plurality of elements (e. g. , resistors and transistors) and a second section having a plurality of elements (e. g. , resistors and transistors). One or more of the elements (e. g. transistors or resistors) in the first and second sections are mismatched to introduce a systematic offset in the transimpedance stage, to make the net input referred offset of the amplification device unidirectional. The feedback device (e. g. an integrator) is coupled to an output of the amplification device and an input of the transimpedance portion to provide a unidirectional offset correction to the amplification device for reduced noise enhancement.

US Patent:

6927631, Aug 9, 2005

Filed:

Aug 23, 2002

Appl. No.:

10/226228

Inventors:

Sandeep Kumar Gupta - Aliso Viejo CA, US
Venugopal Gopinathan - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03F003/45

US Classification:

330260

Abstract:

A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

US Patent:

6952136, Oct 4, 2005

Filed:

Aug 28, 2002

Appl. No.:

10/229175

Inventors:

Sandeep K. Gupta - Aliso Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03F003/08

US Classification:

330308, 250214 A, 330297

Abstract:

A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a plurality of power sources and a bias current portion having a plurality of bias current devices. The system also includes an amplification portion having a plurality of amplifiers. A first group of the plurality of amplifiers is coupled to the power source portion and the bias current portion, such that feedback voltage is substantially eliminated to substantially eliminate oscillations in the amplification portion.

US Patent:

6954162, Oct 11, 2005

Filed:

Oct 19, 2004

Appl. No.:

10/967358

Inventors:

Sandeep K. Gupta - Aliso Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M003/00

US Classification:

341143, 341144

Abstract:

In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock. This configuration: (1) eliminates poles from the transfer function that defines processing of a signal by the high order delta sigma modulator stage, (2) reduces the power consumed by the high order delta sigma modulator stage for a given settling time requirement, (3) facilitates reducing the size of the summing junction switches in the high order delta sigma modulator stage to decrease distortions due to charge injections, and (4) allows a reference signal voltage, which is coupled to a cross coupled feedback switched capacitor network in the integrators, to be set equal to one of two power supply voltages for the high order delta sigma modulator stage, thereby further reducing the power consumed by the delta sigma modulator.