Sandra Ayers Lee

US Patent:

6766428, Jul 20, 2004

Filed:

Apr 6, 2001

Appl. No.:

09/827437

Inventors:

Ashley N. Saulsbury - Los Gatos CA
James E. Kocol - San Diego CA
Sandra C. Lee - Carlsbad CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1300

US Classification:

711154, 711156

Abstract:

One embodiment of the present invention provides a system that facilitates reliable execution in a computer system by keeping track of write operations to a main memory of the computer system in order to undo the write operations if necessary. This system operates by receiving a write operation directed to the main memory at a memory controller, wherein the write operation includes data to be written to the main memory and a write address specifying a location in the main memory into which the data is to be written. Next, the system examines a log bit associated with the write address, wherein the log bit indicates whether an existing value from the write address in main memory has been copied to a checkpoint store. If the log bit is not set, the system creates a new entry for the write address in the checkpoint store; retrieves an existing value from the write address in the main memory; and stores the existing value to the new entry in the checkpoint store. The system then stores the data to be written to write address in the main memory.

US Patent:

6779087, Aug 17, 2004

Filed:

Apr 6, 2001

Appl. No.:

09/827426

Inventors:

Ashley N. Saulsbury - Los Gatos CA
James E. Kocol - San Diego CA
Sandra C. Lee - Carlsbad CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711143, 714 15

Abstract:

One embodiment of the present invention provides a system that facilitates reliable execution in a computer system by periodically checkpointing write operations to a main memory of the computer system. The system operates by receiving a write operation directed to the main memory at a memory controller, wherein the write operation includes data to be written to the main memory and a write address specifying a location in the main memory into which the data is to be written. Next, the system looks up the write address in a checkpoint store coupled to the memory controller. If the write address is not associated with any entry in the checkpoint store, the system creates an entry for the write address in the checkpoint store, and writes the data to be written to the entry. The system then periodically performs a checkpointing operation, which transfers the data to be written from the checkpoint store to the write address in the main memory.

US Patent:

7069149, Jun 27, 2006

Filed:

Dec 14, 2001

Appl. No.:

10/023420

Inventors:

Douglas Francis Goff - Danville CA, US
Luc Vincent - Palo Alto CA, US
Kevin L. Deal - Houston TX, US
William S. Kowalik - La Habra Heights CA, US
Sebastien Bombarde - Oakland CA, US
Sandra Lee - Danville CA, US
William R. Volz - Katy TX, US
Richard C. Jones - Fullerton CA, US

Assignee:

Chevron U.S.A. Inc. - San Ramon CA

International Classification:

G01V 1/28

US Classification:

702 16

Abstract:

A computer implemented method for interpreting faults from a fault-enhanced 3-D seismic attribute cube. The method includes the steps of extracting faults from a 3-D seismic attribute cube, and of calculating a minimum path value for each voxel of the 3-D seismic attribute cube. A fault network skeleton is extracted from the 3-D seismic attribute cube by utilizing the minimum path values which correspond to voxels within the 3-D seismic attribute cube. The individual fault networks are then labeled, and a vector description of the fault network skeleton is created. The fault network skeleton is subdivided into individual fault patches wherein the individual fault patches are the smallest, non-intersecting, non-bifurcating patches that lie on only one geologic fault. The individual fault patches are then correlated into a representation of geologic faults.

US Patent:

47570261, Jul 12, 1988

Filed:

Sep 16, 1987

Appl. No.:

7/097539

Inventors:

Been-Jon Woo - Saratoga CA
Mark A. Holler - Palo Alto CA
Ender Hokelek - Santa Clara CA
Sandra S. Lee - Los Altos CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21265

US Classification:

437 29

Abstract:

A method of forming complementary metal oxide semiconductor field-effect transistors (CMOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effects, to increase punch through voltage and to increase gate-aided breakdown voltage.

US Patent:

47286172, Mar 1, 1988

Filed:

Nov 4, 1986

Appl. No.:

6/926733

Inventors:

Been-Jon Woo - Saratoga CA
Mark A. Holler - Palo Alto CA
Ender Hokelek - Santa Clara CA
Sandra S. Lee - Los Altos CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21265

US Classification:

437 30

Abstract:

A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.

US Patent:

47849657, Nov 15, 1988

Filed:

Sep 16, 1987

Appl. No.:

7/097532

Inventors:

Been-Jon Woo - Saratoga CA
Mark A. Holler - Palo Alto CA
Sandra S. Lee - Los Altos CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21265

US Classification:

437 30

Abstract:

A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.

US Patent:

52565947, Oct 26, 1993

Filed:

Jun 16, 1989

Appl. No.:

7/367547

Inventors:

Albert T. Wu - San Jose CA
Shinji Nozaki - Tokyo, JP
Thomas George - Albany CA
Sandra S. Lee - Los Altos CA
Masayoshi Umeno - Nagoya, JP

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21205

US Classification:

437 89

Abstract:

A process for forming GaAs on a silicon substrate with very low levels of unintended silicon doping. First, a dielectric layer of silicon dioxide, silicon nitride, or both is grown or deposited on the substrate. Next, a window is opened in the dielectric layer exposing the silicon substrate in the regions in which the GaAs is to be formed. The GaAs layer is then formed on the substrate using conventional techniques with the gas phase transfer of silicon contamination from the edges and back of the silicon substrate to the GaAs region inhibited by the dielectric layer or layers.