Sarah Elizabeth Mann

US Patent:

20130173996, Jul 4, 2013

Filed:

Dec 30, 2011

Appl. No.:

13/341833

Inventors:

Michael H. Anderson - Los Angeles CA, US
Sarah Mann - Tucson AZ, US

International Classification:

H03M 13/05
G06F 11/10

US Classification:

714770, 714E11034

Abstract:

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

US Patent:

20150012796, Jan 8, 2015

Filed:

Mar 24, 2014

Appl. No.:

14/223740

Inventors:

- Los Angeles CA, US
Sarah Mann - Tucson AZ, US

Assignee:

STREAMSCALE, INC. - Los Angeles CA

International Classification:

H03M 13/00
H03M 13/37

US Classification:

714763

Abstract:

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.