Scott J Alberhasky

US Patent:

20130082320, Apr 4, 2013

Filed:

Sep 30, 2011

Appl. No.:

13/249529

Inventors:

Scott J. Alberhasky - Portland OR, US
David E. Hart - Cornelius OR, US
Sudarsan Uppili - Portland OR, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 29/78
H01L 21/336

US Classification:

257329, 438268, 257E29262, 257E2141

Abstract:

Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.

US Patent:

20130082321, Apr 4, 2013

Filed:

Sep 30, 2011

Appl. No.:

13/249594

Inventors:

Harmeet Sobti - Portland OR, US
Timothy K. McGuire - Beaverton OR, US
David L. Snyder - Beaverton OR, US
Scott J. Alberhasky - Portland OR, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 29/78
H01L 21/336

US Classification:

257329, 438268, 257E29262, 257E2141

Abstract:

Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance.

US Patent:

20130087850, Apr 11, 2013

Filed:

Oct 11, 2011

Appl. No.:

13/270780

Inventors:

Scott J. Alberhasky - Portland OR, US
David Harper - Battle Ground WA, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 27/088
H01L 21/336

US Classification:

257329, 438268, 257E2706, 257E2141

Abstract:

Semiconductor devices that include a trench with conductive material for connecting a VDMOS device to a LDMOS device are described. The semiconductor devices include a substrate having a first region and a second region, wherein the second region is disposed on the first region. A trench extends from a top surface of the second region to the first region. The semiconductor substrate includes a VDMOS device formed proximate to the top surface of the second region and a LDMOS device that is also formed proximate to the top surface of the second region. The drain region of the VDMOS device is electrically connected to the source region of the LDMOS device by way of a conductive material disposed in the trench.