Scott Earl Allen

US Patent:

6686616, Feb 3, 2004

Filed:

May 10, 2000

Appl. No.:

09/567717

Inventors:

Scott T. Allen - Apex NC
John W. Palmour - Raleigh NC
Terrence S. Alcorn - Apex NC

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 2980

US Classification:

257280, 257 77, 257284, 257287, 257472

Abstract:

SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs.

US Patent:

7067361, Jun 27, 2006

Filed:

Nov 12, 2003

Appl. No.:

10/706641

Inventors:

Scott T. Allen - Apex NC, US
John W. Palmour - Raleigh NC, US
Terrence S. Alcorn - Apex NC, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 21/338

US Classification:

438167, 438172, 438571

Abstract:

SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs.

US Patent:

7135747, Nov 14, 2006

Filed:

Feb 25, 2004

Appl. No.:

10/786962

Inventors:

Scott Thomas Allen - Apex NC, US
James William Milligan - Cary NC, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 29/94

US Classification:

257401, 257287, 257390, 257E2707

Abstract:

A high power, high frequency semiconductor device has a plurality of unit cells connected in parallel. The unit cells each having a controlling electrode and first and second controlled electrodes. A thermal spacer divides at least one of the unit cells into a first active portion and a second active portion, spaced apart from the first potion by the thermal spacer. The controlling electrode and the first and second controlled electrodes of the unit cell cross over the first thermal spacer.

US Patent:

7211833, May 1, 2007

Filed:

Jan 20, 2005

Appl. No.:

11/039566

Inventors:

Bradley E. Williams - Cary NC, US
Peter S. Andrews - Durham NC, US
John A. Edmond - Cary NC, US
Scott T. Allen - Apex NC, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 33/00

US Classification:

257 98, 257 99, 257751, 257E33068

Abstract:

Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a reflector layer, on the epitaxial region. A barrier layer is provided on the reflector layer and extending on a sidewall of the reflector layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers.

US Patent:

7348612, Mar 25, 2008

Filed:

Oct 29, 2004

Appl. No.:

10/977054

Inventors:

Saptharishi Sriram - Cary NC, US
Scott Allen - Apex NC, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 31/112

US Classification:

257288, 257E28061, 438286

Abstract:

The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a MESFET having a source region, a drain region and a gate contact. The gate contact is disposed between the source region and the drain region. The drain region is electrically coupled to the substrate through a contact via hole to the substrate. Related methods of fabricating MESFETs are also provided herein.

US Patent:

7525122, Apr 28, 2009

Filed:

Jun 29, 2005

Appl. No.:

11/169378

Inventors:

Zoltan Ring - Durham NC, US
Helmut Hagleitner - Zebulon NC, US
Jason Patrick Henning - Carrboro NC, US
Andrew Mackenzie - Cary NC, US
Scott Allen - Apex NC, US
Scott Thomas Sheppard - Chapel Hill NC, US
Richard Peter Smith - Carrboro NC, US
Saptharishi Sriram - Cary NC, US
Allan Ward, III - Durham NC, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 29/15
H01L 31/0256

US Classification:

257 76, 257 99, 257E29104

Abstract:

A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.

US Patent:

7611915, Nov 3, 2009

Filed:

Mar 20, 2007

Appl. No.:

11/688605

Inventors:

Bradley E. Williams - Cary NC, US
Peter S. Andrews - Durham NC, US
John A. Edmond - Cary NC, US
Scott T. Allen - Apex NC, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 21/00

US Classification:

438 27, 438 29, 438653, 257 98, 257 99, 257751, 257E33068, 257E33069

Abstract:

Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a reflector layer, on the epitaxial region. A barrier layer is provided on the reflector layer and extending on a sidewall of the reflector layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers.

US Patent:

7970891, Jun 28, 2011

Filed:

Jan 17, 2007

Appl. No.:

11/624129

Inventors:

Scott T. Allen - Mountain View CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

G06F 15/173
G06Q 30/10
H04N 7/10
H04N 7/025

US Classification:

709224, 705 1441, 705 1445, 725 34

Abstract:

The present disclosure includes a system and method for tracking links displayed in Web browsers. In some implementations, a method includes receiving a hostname operable to identify an action and an instance of a link displayed through a Web browser. The hostname is unique for a period of time. The one or more actions associated with the displayed link are tracked.