Scott Gerard Balster from 13235 Rolling Hills Ln, Dallas, TX 75240, age 55, Phone: 9729808581

Resumes

Process Development Manager

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Location:

Dallas, TX

Industry:

Semiconductors

Work:

Honeywell Sep 1997 - Oct 1999
Process Development Engineer
Texas Instruments Sep 1997 - Oct 1999
Process Development Manager

Education:

Arizona State University 1993 - 1997
Doctorates, Doctor of Philosophy, Electronics Engineering, Philosophy Arizona State University 1990 - 1993
Masters, Electronics Engineering

Scott Balster

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Us Patents

Stacked Capacitor And Method Of Fabricating Same
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US Patent:

7312119, Dec 25, 2007
Filed:

Oct 13, 2006
Appl. No.:

11/549248
Inventors:

Scott Gerard Balster - Dallas TX, US
Badih El-Kareh - Cedar Park TX, US
Philipp Steinman - Richardson TX, US
Christoph Dirnecker - Haag, DE
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 21/8242
H01L 21/20
US Classification:

438253, 438396, 257E21008
Abstract:

The invention relates to a stacked capacitor () comprising a silicon base plate (), a poly-silicon center plate () arranged above the base plate (), a lower gate-oxide dielectric () arranged between the base plate () and the center plate (), a cover plate () made of a metallic conductor and arranged above the center plate (), and an upper dielectric () arranged between the center plate () and the cover plate (). The cover plate () and the base plate () are electrically connected to each other and together form a first capacitor electrode. The center plate () forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.

Integrated Bicmos Semiconductor Circuit
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US Patent:

7498639, Mar 3, 2009
Filed:

Sep 23, 2005
Appl. No.:

11/233960
Inventors:

Philipp Steinmann - Unterschleissheim, DE
Scott Balster - Dallas TX, US
Badih El-Kareh - Cedar Park TX, US
Thomas Scharnagl - Tiefenbach, DE
Michael Schmitt - Haag a.d. Amper, DE
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 31/112
US Classification:

257370, 257374, 257E21434, 438445
Abstract:

An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.

Advanced Cmos Using Super Steep Retrograde Wells
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US Patent:

7501324, Mar 10, 2009
Filed:

Apr 27, 2006
Appl. No.:

11/380602
Inventors:

Jeffrey A. Babcock - Richardson TX, US
Angelo Pinto - Allen TX, US
Scott Balster - Dallas TX, US
Alfred Haeusler - Freising, DE
Gregory E. Howard - Dallas TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 21/336
US Classification:

438289, 438527
Abstract:

The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer () beneath the gate dielectric () and source and drain regions () of a MOS transistor. The carbon containing layer () will prevent the diffusion of dopants into the region () directly beneath the gate dielectric layer ().

Advanced Cmos Using Super Steep Retrograde Wells
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US Patent:

7655523, Feb 2, 2010
Filed:

Oct 30, 2007
Appl. No.:

11/928652
Inventors:

Jeffrey A. Babcock - Richardson TX, US
Angelo Pinto - Allen TX, US
Scott Balster - Dallas TX, US
Alfred Haeusler - Freising, DE
Gregory E. Howard - Dallas TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 21/336
US Classification:

438289, 257E21618
Abstract:

The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer () beneath the gate dielectric () and source and drain regions () of a MOS transistor. The carbon containing layer () will prevent the diffusion of dopants into the region () directly beneath the gate dielectric layer ().

Silicide Block Isolated Junction Field Effect Transistor Source, Drain And Gate
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US Patent:

7670890, Mar 2, 2010
Filed:

Jul 26, 2006
Appl. No.:

11/493229
Inventors:

Badih El-Kareh - Cedar Park TX, US
Hiroshi Yasuda - Munich, DE
Scott Gerard Balster - Dallas TX, US
Philipp Steinmann - Unterschleissheim, DE
Joe R. Trogolo - Plano TX, US
Assignee:

Texas Instruments Deutschland GmbH - Freising
Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 29/80
H01L 21/337
US Classification:

438188, 438186, 438196, 257256, 257274, 257E21421
Abstract:

An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.

Method Of Fabricating An Integrated Circuit With Gate Self-Protection, And An Integrated Circuit With Gate Self-Protection
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US Patent:

7772057, Aug 10, 2010
Filed:

Sep 7, 2006
Appl. No.:

11/470760
Inventors:

Badih El-Kareh - Cedar Park TX, US
Scott Gerard Balster - Dallas TX, US
Hiroshi Yasuda - Plano TX, US
Manfred Schiekofer - Freising, DE
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 21/337
US Classification:

438189, 438190, 257133, 257131
Abstract:

An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.

Method For Fabricating Isolated Integrated Semiconductor Structures
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US Patent:

8012842, Sep 6, 2011
Filed:

Jun 12, 2008
Appl. No.:

12/137817
Inventors:

Scott Balster - Dallas TX, US
Badih El-Kareh - Cedar Park TX, US
Hiroshi Yasuda - Plano TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 21/331
US Classification:

438353, 438354, 257338, 257E27015, 257E21356
Abstract:

An integrated semiconductor structure that has first and second bipolar transistor structures. The first bipolar transistor structure has a doped tank region in contact with a doped tank region located underneath a contacting sinker. The second bipolar transistor structure has a doped buried region that is the same dopant type as its doped tank region. A method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer. A first patterned photomask is used to form a doped buried region and a doped tank region within the first bipolar transistor structure. A second patterned photomask is used to form a doped buried region and a doped tank region within the second bipolar transistor, plus a doped buried region and a doped tank region underneath a contacting sinker adjacent to the first bipolar transistor.

Advanced Cmos Using Super Steep Retrograde Wells
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US Patent:

8129246, Mar 6, 2012
Filed:

Jan 13, 2011
Appl. No.:

13/006224
Inventors:

Jeffrey A. Babcock - Richardson TX, US
Angelo Pinto - Allen TX, US
Scott Balster - Dallas TX, US
Alfred Haeusler - Freising, DE
Gregory E. Howard - Dallas TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 21/336
US Classification:

438289, 438527
Abstract:

The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer () beneath the gate dielectric () and source and drain regions () of a MOS transistor. The carbon containing layer () will prevent the diffusion of dopants into the region () directly beneath the gate dielectric layer ().