Scott Robert Doyle

US Patent:

6487134, Nov 26, 2002

Filed:

Aug 9, 2001

Appl. No.:

09/927059

Inventors:

Nandor G. Thoma - Manassas VA
Scott E. Doyle - Centreville VA

Assignee:

BAE Systems Information and Electronic Systems Integration, Inc. - Nashua NH

International Classification:

G11C 700

US Classification:

365205, 365207, 365208, 36518905, 327 51, 327 57

Abstract:

A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series. The second set of dual-path inverters is coupled to the second set of isolation transistors, and the second set of dual-path inverters includes a fifth transistor connected to a sixth transistor in series along with a seventh transistor connected to an eighth transistor in series. The isolation transistor couples the first and second sets of dual-path inverters to ground.

US Patent:

6717233, Apr 6, 2004

Filed:

Jan 25, 2000

Appl. No.:

09/491230

Inventors:

Nadim Haddad - Oakton VA
Charles N. Alcorn - Centreville VA
Jonathan Maimon - Manassas VA
Leonard R. Rockett - Washington D. C. WA
Scott Doyle - Centreville VA

Assignee:

BAE Systems Information and Electronic Systems Integration, Inc. - Nashua NH

International Classification:

H01L 2900

US Classification:

257536, 257379, 257380, 257381, 257538

Abstract:

A method for fabricating resistors within a semiconductor integrated circuit device is disclosed. A resistor is fabricated by first depositing a passivation layer on a semiconductor substrate having multiple transistors previously formed thereon. Next, a first contact window and a second contact window are formed through the first passivation layer at a first contact location and a second contact location, respectively. The first and second contact windows are then filled with metal, such as tungsten, and the metal at the first and second contact windows is planarized to form a first bottom contact and a second bottom contact, respectively. A resistive film, such as polysilicon, subsequently deposited over the first passivation layer. Next, a second passivation layer is formed over the resistive film. Finally, a first top contact and a second top contact are formed to respectively connect the first bottom contact and the second bottom contact to the resistive film.

US Patent:

7269057, Sep 11, 2007

Filed:

Apr 27, 2005

Appl. No.:

11/116024

Inventors:

Nadim F. Haddad - Oakton VA, US
Neil E. Wood - Centreville VA, US
Adam Bumgarner - Woodbridge VA, US
Wayne Neiderer - Manassas VA, US
Shankarnarayana Ramaswamy - Chantilly VA, US
Scott Doyle - Centreville VA, US
Tri-Minh Hoang - Clifton VA, US

Assignee:

BAE Systems Information And Electronic Systems Integration Inc. - Nashua NH

International Classification:

G11C 11/00

US Classification:

365156, 365154, 257903

Abstract:

A method for connecting circuit elements within an integrated circuit for reducing single-event upsets is disclosed. The integrated circuit includes a first and second circuit elements that are substantially identical to each other. In order to reduce the single-event upsets to the first and second circuit elements, each of the first and second circuit elements is divided into a first sub-element and a second sub-element. The first sub-element of the first circuit element is connected to the second sub-element of the second circuit element. The second sub-element of the first circuit element is connected to the first sub-element of the second circuit element. As a result, the nodal spacings between the sub-elements within the first and second circuit elements are effectively increased without demanding additional real estate.

US Patent:

20060133134, Jun 22, 2006

Filed:

Dec 16, 2004

Appl. No.:

11/014315

Inventors:

Scott Doyle - Centreville VA, US
Nandor Thoma - Vero Beach FL, US

International Classification:

G11C 11/00

US Classification:

365154000

Abstract:

A single-event upset tolerant random access memory cell is disclosed. The single-event upset tolerant memory cell includes a first and second sets of access transistors along with a first and second sets of dual-path inverters. The first set of access transistors is coupled to a first bitline, and the second set of access transistors is coupled to a second bitline that is complementary to the first bitline. The first set of dual-path inverters, which is coupled to the first set of access transistors, includes a first transistor connected to a second transistor in series and a third transistor connected to a fourth transistor in series. The second set of dual-path inverters, which is coupled to the second set of access transistors, includes a fifth transistor connected to a sixth transistor in series and a seventh transistor connected to an eighth transistor in series.

US Patent:

61697028, Jan 2, 2001

Filed:

May 26, 1999

Appl. No.:

9/320207

Inventors:

Tri Minh Hoang - Clifton VA
Livia Zien - Manassas VA
Scott Doyle - Centreville VA
David Lawson - Harwood VA

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

G11C 800

US Classification:

36523006

Abstract:

A memory device includes a plurality of address on-chip receivers (OCRs), an address decoder coupled to the address OCRs, a plurality of first delay circuits coupled between the address OCRs and the address decoder, and a plurality of chip select bypass circuits. Each chip select bypass circuit is respectively coupled to one of the plurality of first delay circuits for initially reducing a delay therein responsive to a control signal. The chip select bypass circuit includes a second delay circuit having a delay less than the first delay circuit, and a disable circuit. The disable circuit disables the first delay circuit and selectively couples the second delay circuit in place of the first delay circuit responsive to the control signal.

US Patent:

61816418, Jan 30, 2001

Filed:

May 26, 1999

Appl. No.:

9/320227

Inventors:

Dongho Lee - Manassas VA
Tri Minh Hoang - Clifton VA
Livia Zien - Manassas VA
Scott Doyle - Centreville VA
David Lawson - Harwood VA

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

G11C 800

US Classification:

3652335

Abstract:

A memory device includes a plurality of memory cells arranged in rows and columns. The memory cells are divided into a plurality of sub-arrays. The memory cell further includes a plurality of word lines connecting rows of the memory cells, and a plurality of bit line pairs connecting columns of the memory cells. An address transition detect (ATD) circuit detects an address transition for a selected memory cell and generates an ATD pulse in response thereto. A respective bit line precharge circuit is associated with each of the plurality of sub-arrays. An ATD pulse distribution circuit distributes the ATD pulse to only a selected sub-array containing the selected memory cell to activate only the bit line precharge circuit of the selected sub-array and not activate precharge circuits of other non-selected sub-arrays.