Scott E Harper

US Patent:

20230087217, Mar 23, 2023

Filed:

Sep 22, 2022

Appl. No.:

17/950341

Inventors:

- Blacksburg VA, US
Scott HARPER - Blacksburg VA, US
Jonathan GRAF - Blacksburg VA, US
Carlton FRALEY - Christiansburg VA, US
Alan COOK - Christiansburg VA, US
Timothy DUNHAM - Roanoke VA, US

International Classification:

H04L 9/00
G06F 30/31
H04L 9/32

Abstract:

A computer system traces an original electronic design automation (EDA) implementation process for electronic hardware designs. The original EDA implementation process includes multiple subprocesses to convert a hardware model to a physically-realized electronic circuit. The system inputs a cryptographic key and design information that includes the hardware model, constraints, properties, implementation settings, and other directives for directing the conversion. The cryptographic key and design information are processed to generate a sequence of instructions to execute and provide traceability of each subprocess. For each subprocess, the system gathers intermediate design state and implementation settings resulting from or influencing execution of the subprocess; combines the intermediate design state and implementation settings into a data string and determines a cryptographic hash value for the data string; digitally signs the cryptographic hash value using a digital signature certificate derived from the cryptographic key to generate a signed hash; stores the signed hash and identifiers associated with data files used for determining the cryptographic hash value to an electronic ledger to generate an updated electronic ledger; authenticates the signed hash from the electronic ledger to generate an authenticated signed hash; reconstructs a hash from the data files stored in the electronic ledger to generate a reconstructed hash; compares the authenticated signed hash with the reconstructed hash, and in response to a mismatch, generates an error signal. The steps are repeated for each subsequent subprocess, and the traced EDA implementation process results are stored in memory.

US Patent:

20210117556, Apr 22, 2021

Filed:

Dec 28, 2020

Appl. No.:

17/134704

Inventors:

- Blacksburg VA, US
Ali Asgar Ali Akbar SOHANGHPURWALA - Blacksburg VA, US
Scott Jeffery HARPER - Blacksburg VA, US

International Classification:

G06F 21/60
H04L 9/06
G06F 21/62
G06F 21/76
G06F 21/57
H04L 9/08
G09C 1/00

Abstract:

An apparatus, method, and system assess the trustworthiness of a design representation while maintaining its confidentiality and thwarting attempts at unauthorized access, misappropriation, and reverse engineering of confidential proprietary aspects of the design representation and/or its bit stream. A utility/tool is provided for trust assessment and verification of designs and/or bit streams. The utility/tool may be instantiated on a semiconductor device or implemented as a utility executable on a mobile computing device or other information processing system, apparatus, or network.

US Patent:

20190065757, Feb 28, 2019

Filed:

Aug 25, 2017

Appl. No.:

15/686661

Inventors:

- Blacksburg VA, US
Ali Asgar Ali Akbar SOHANGHPURWALA - Blacksburg VA, US
Scott Jeffery HARPER - Blacksburg VA, US

International Classification:

G06F 21/60
H04L 9/06

Abstract:

An apparatus, method and system are disclosed which may be used for assessing the trustworthiness of a particular proprietary microelectronics device design representation in a manner that will maintain its confidentiality and, among other things, thwart attempts at unauthorized access, misappropriation and reverse engineering of the confidential proprietary aspects contained in the design representation and/or its bit stream design implementation format. The disclosed method includes performing a process for assessing/verifying a particular microelectronics device design representation and then providing some indication of the trustworthiness of that representation. An example utility/tool which implements the disclosed method is described that is particularly useful for trust assessment and verification of FPGA designs. The described utility/tool may be instantiated on a semiconductor device or implemented as a software utility executable on a mobile computing device or other information processing system, apparatus or network.