Scott P Hellenbach

US Patent:

7676649, Mar 9, 2010

Filed:

Oct 3, 2005

Appl. No.:

11/243507

Inventors:

John Rapp - Manassas VA, US
Chandan Mathur - Manassas VA, US
Scott Hellenbach - Amissville VA, US
Mark Jones - Centreville VA, US
Joseph A. Capizzi - Sterling VA, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

G06F 15/76
G06F 11/00
G06F 11/16
G06F 9/00

US Classification:

712 43, 712228, 714 6, 714 10, 714 11

Abstract:

According to an embodiment of the invention, a computing machine comprises a pipeline accelerator, a host processor coupled to the pipeline accelerator, and a redundant processor, a redundant pipeline unit, or both, coupled to the host processor and to the pipeline accelerator. The computing machine may also include a system-restore server and a system-restore bus that allow the machine to periodically save the machine states in case of a failure. Such a computing machine has a fault-tolerant scheme that is often more flexible than conventional schemes. For example, if the pipeline accelerator has more extra “space” than the host processor, then one can add to the computing machine one or more redundant pipeline units that can provide redundancy to both the pipeline and the host processor. Therefore, the computing machine can include redundancy for the host processor even though it has no redundant processing units.

US Patent:

7809982, Oct 5, 2010

Filed:

Oct 3, 2005

Appl. No.:

11/243508

Inventors:

John Rapp - Manassas VA, US
Chandan Mathur - Manassas VA, US
Scott Hellenbach - Amissville VA, US
Mark Jones - Centreville VA, US
Joseph A. Capizzi - Sterling VA, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

G06F 11/00

US Classification:

714 10, 714 31

Abstract:

A computing machine comprises an electronic circuit operable to perform a function, a programmable integrated circuit such as an FPGA, and a processor. The processor is operable to detect a failure of the electronic circuit and to configure the programmable integrated circuit to perform the function of the electronic circuit in response to detecting the failure. Alternatively, the computing machine comprises a hardwired pipeline operable to perform a function and a processor operable to detect a failure of the pipeline and to perform the function in response to detecting the failure. By allowing a first type of circuit (e. g. , an FPGA) to take over for a failed second type of circuit (e. g. , a processor), such a computing machine can be fault-tolerant without having redundant versions of each component, and may thus be less expensive and smaller than computing machines of comparable computing power.

US Patent:

7987341, Jul 26, 2011

Filed:

Oct 9, 2003

Appl. No.:

10/684053

Inventors:

Chandan Mathur - Manassas VA, US
Scott Hellenbach - Amissville VA, US
John W. Rapp - Manassas VA, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

G06F 9/00
G06F 15/76
G06F 3/00

US Classification:

712 34, 710 52

Abstract:

A computing machine includes a first buffer and a processor coupled to the buffer. The processor executes an application, a first data-transfer object, and a second data-transfer object, publishes data under the control of the application, loads the published data into the buffer under the control of the first data-transfer object, and retrieves the published data from the buffer under the control of the second data-transfer object. Alternatively, the processor retrieves data and loads the retrieved data into the buffer under the control of the first data-transfer object, unloads the data from the buffer under the control of the second data-transfer object, and processes the unloaded data under the control of the application. Where the computing machine is a peer-vector machine that includes a hardwired pipeline accelerator coupled to the processor, the buffer and data-transfer objects facilitate the transfer of data between the application and the accelerator.

US Patent:

20040133763, Jul 8, 2004

Filed:

Oct 9, 2003

Appl. No.:

10/684102

Inventors:

Chandan Mathur - Manassas VA, US
Scott Hellenbach - Amissville VA, US
John Rapp - Manassas VA, US
Larry Jackson - Manassas VA, US
Mark Jones - Centreville VA, US
Troy Cherasaro - Culpeper VA, US

Assignee:

Lockheed Martin Corporation

International Classification:

G06F015/00

US Classification:

712/034000

Abstract:

A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline accelerator generates pipeline data from the host data. Alternatively, the pipeline accelerator generates the pipeline data, and the host processor generates the host data from the pipeline data. Because the peer-vector machine includes both a processor and a pipeline accelerator, it can often process data more efficiently than a machine that includes only processors or only accelerators. For example, one can design the peer-vector machine so that the host processor performs decision-making and non-mathematically intensive operations and the accelerator performs non-decision-making and mathematically intensive operations. By shifting the mathematically intensive operations to the accelerator, the peer-vector machine often can, for a given clock frequency, process data at a speed that surpasses the speed at which a processor-only machine can process the data.

US Patent:

20060085781, Apr 20, 2006

Filed:

Oct 3, 2005

Appl. No.:

11/243506

Inventors:

John Rapp - Manassas VA, US
Scott Hellenbach - Amissville VA, US
T. Kurian - Manassas VA, US
D. Schooley - Manassas VA, US

International Classification:

G06F 17/50
H03K 19/00

US Classification:

716017000

Abstract:

A library includes one or more circuit templates and an interface template. The one or more circuit templates each define a respective circuit operable to execute a respective algorithm or portion thereof. And the interface template defines a hardware layer operable to interface one of the circuits to pins of a programmable logic circuit when the layer and the one circuit are instantiated on the programmable logic circuit. Such a library may shorten the time and reduce the effort that an engineer expends designing a circuit for instantiation on a PLIC or ASIC by allowing the engineer to build the circuit from templates of previously designed and debugged circuits.

US Patent:

20060101250, May 11, 2006

Filed:

Oct 3, 2005

Appl. No.:

11/243459

Inventors:

John Rapp - Manassas VA, US
Chandan Mathur - Manassas VA, US
Scott Hellenbach - Amissville VA, US
Mark Jones - Centreville VA, US
Joseph Capizzi - Sterling VA, US

International Classification:

G06F 9/44

US Classification:

712226000

Abstract:

A computing machine includes programmable integrated circuits, a configuration registry, and a processor. The registry stores a file that defines a circuit having portions, and the processor is, in response to the file, operable to instantiate one of the circuit portions on one of the programmable integrated circuits. Consequently, by accessing a file that defines a circuit, such a computing machine can often instantiate the circuit on a pipeline accelerator regardless of the hardware that compose the accelerator and despite modifications to the circuit or to the hardware. That is, the computing machine can often “fit” the circuit into the pipeline accelerator regardless of its composition.

US Patent:

20060230377, Oct 12, 2006

Filed:

Oct 3, 2005

Appl. No.:

11/243509

Inventors:

John Rapp - Manassas VA, US
Scott Hellenbach - Amissville VA, US
T. Kurian - Manassas VA, US
D. Schooley - Manassas VA, US
Troy Cherasaro - Culpeper VA, US

International Classification:

G06F 17/50

US Classification:

716018000

Abstract:

A computer-based circuit-design tool includes a front end, an interpreter coupled to the front end, and a generator coupled the interpreter. The front end receives symbols that define an algorithm, and the interpreter parses the algorithm into respective algorithm portions. The generator identifies a corresponding circuit template for each of the algorithm portions, each template defining a circuit for executing the respective algorithm portion, and interconnects the identified templates such that the interconnected templates define a circuit that is operable to execute the algorithm. As compared to prior design tools, this tool may decrease the time and effort required to design a circuit for instantiation on a programmable logic integrated circuit (PLIC) or on an application-specific integrated circuit (ASIC) by allowing one to construct the circuit from previously written templates that define previously tested and debugged circuits.