Scott L Jacobs

US Patent:

20030038378, Feb 27, 2003

Filed:

Apr 12, 2001

Appl. No.:

09/834014

Inventors:

Scott Jacobs - Pittsboro NC, US

Assignee:

Virtual Integration, Inc. - Pittsboro NC

International Classification:

H01L023/48
H01L023/52

US Classification:

257/783000, 257/782000, 257/778000

Abstract:

Microelectronic packages may be fabricated by forming a release layer on a process substrate. A thin film decal is formed on the release layer. The thin film decal includes first and second opposing decal faces, first decal input/output pads on the first decal face, second decal input/output pads on the second decal face and at least one internal wiring layer that electrically connects at least one of the first and second decal input/output pads. The first decal input/output pads are adjacent the release layer and the second decal input/output pads are remote from the release layer. A dielectric adhesive layer is then formed on the second decal face. The dielectric adhesive layer includes first and second opposing dielectric layer faces and conductive vias therein that extend between the first and second opposing dielectric adhesive layer faces. The first dielectric adhesive layer face is adjacent the second decal face and the second adhesive dielectric layer face is remote from the second decal face, such that at least one of the conductive vias electrically connects to at least one of the second decal input/output pads. The dielectric adhesive layer second face is then adhesively bonded to a second level substrate, such as a printed circuit board, that includes second level substrate input/output pads on a face thereof, such that at least one of the conductive vias electrically connects to at least one of the second level substrate input/output pads. The release layer is processed, for example dissolved, to thereby release the process substrate from on the first face of the thin film decal. A first level substrate, such as an integrated circuit chip, is then bonded to the first face of the thin film decal, for example by solder bump reflow.

US Patent:

20120097971, Apr 26, 2012

Filed:

Oct 25, 2011

Appl. No.:

13/281356

Inventors:

Scott L. Jacobs - Pittsboro NC, US

International Classification:

H01L 29/20
H01L 21/306
H01L 29/06

US Classification:

257 76, 257618, 438689, 257E29022, 257E29089, 257E21215

Abstract:

Substrates are processed, with a high degree of topography, to produce a variety of semiconductors or other devices and are then stretched out, substantially flat, to achieve a significant increase in surface area. Devices made from a contiguous structure of a single, active crystalline material or from non-contiguous structures of multiple materials, such as a combination of dielectrics, thin film metals and active crystalline semiconductors, are fabricated by utilizing anisotropically etched, high aspect ratio configurations of the active material. The structure is then stretched out to achieve a significant increase in surface area, thereby enabling a substantial reduction in the cost of the substrate materials per unit area in the final product.

US Patent:

48289647, May 9, 1989

Filed:

Sep 4, 1987

Appl. No.:

7/093360

Inventors:

William R. Brunsvold - Poughkeepsie NY
Willard E. Conley - Cornwall NY
Scott L. Jacobs - Apex NC
George L. Mack - Pleasant Valley NY
David P. Merritt - Cold Spring NY
Ann M. Uptmor - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03C 190
G03C 516

US Classification:

430271

Abstract:

A composition for use in a process for the deposition of patterned thin metal films on integrated circuit substrates, the composition comprising an admixture of a thermoplastic polyimide resin and a coumarin dye dissolved in a substituted phenol solvent. Optionally a polar solvent having a boiling point greater than 160. degree. C. and a low boiling organic compound (70. degree. -150. degree. C. ) may be incorporated in the composition.

US Patent:

6294407, Sep 25, 2001

Filed:

May 5, 1999

Appl. No.:

9/306463

Inventors:

Scott L. Jacobs - Pittsboro NC

Assignee:

Virtual Integration, Inc. - Pittsboro NC

International Classification:

H01L 2144
H01L 2148
H01L 2150

US Classification:

438118

Abstract:

Microelectronic packages may be fabricated by forming a release layer on a process substrate. A thin film decal is formed on the release layer. The thin film decal includes first and second opposing decal faces, first decal input/output pads on the first decal face, second decal input/output pads on the second decal face and at least one internal wiring layer that electrically connects at least one of the first and second decal input/output pads. The first decal input/output pads are adjacent the release layer and the second decal input/output pads are remote from the release layer. A dielectric adhesive layer is then formed on the second decal face. The dielectric adhesive layer includes first and second opposing dielectric layer faces and conductive vias therein that extend between the first and second opposing dielectric adhesive layer faces. The first dielectric adhesive layer face is adjacent the second decal face and the second adhesive dielectric layer face is remote from the second decal face, such that at least one of the conductive vias electrically connects to at least one of the second decal input/output pads. The dielectric adhesive layer second face is then adhesively bonded to a second level substrate, such as a printed circuit board, that includes second level substrate input/output pads on a face thereof, such that at least one of the conductive vias electrically connects to at least one of the second level substrate input/output pads.

US Patent:

50559079, Oct 8, 1991

Filed:

Jan 25, 1989

Appl. No.:

7/301972

Inventors:

Scott L. Jacobs - Apex NC

Assignee:

Mosaic, Inc. - San Diego CA

International Classification:

H01L 2348

US Classification:

357 71

Abstract:

A low cost, lightweight, fast, dense and reliable extended integration semiconductor structure is provided by forming a thin film multilayer wiring decal on a support substrate and aligning and attaching one or more integrated chips to the decal. A support ring is attached to the decal surrounding the aligned and attached integrated substrate, and the support substrate is removed. Reach-through vias connect the decal wiring to the chips.

US Patent:

51927160, Mar 9, 1993

Filed:

Jul 24, 1991

Appl. No.:

7/735340

Inventors:

Scott L. Jacobs - Apex NC

Assignee:

Polylithics, Inc. - San Diego CA

International Classification:

H01L 2160

US Classification:

437209

Abstract:

A low cost, lightweight, fast, dense and reliable extended integration semiconductor structure is provided by forming a thin film multilayer wiring decal on a support substrate and aligning and attaching one or more integrated chips to the decal. A support ring is attached to the decal surrounding the aligned and attached integrated substrate, and the support substrate is removed. Reach-through vias connect the decal wiring to the chips.

US Patent:

53252659, Jun 28, 1994

Filed:

Jan 7, 1992

Appl. No.:

7/819571

Inventors:

Iwona Turlik - Raleigh NC
Arnold Reisman - Raleigh NC
Deepak Nayak - Los Angeles CA
Giora Dishon - Jerusalem, IL
Scott L. Jacobs - Apex NC
Robert F. Darveaux - Raleigh NC
Neil M. Poley - Cary NC

Assignee:

MCNC - Research Triangle Park NC
IBM Corporation - Armonk NY
Northern Telecom Limited - Montreal

International Classification:

H05K 720

US Classification:

361702

Abstract:

A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.

US Patent:

48170933, Mar 28, 1989

Filed:

Jun 18, 1987

Appl. No.:

7/064976

Inventors:

Scott L. Jacobs - Apex NC
Maurice T. McMahon - Poughkeepsie NY
Perwaiz Nihal - Hopewell Junction NY
Burhan Ozmat - Dallas TX
Henri D. Schnurmann - Monsey NY
Arthur R. Zingher - White Plains NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

371 25

Abstract:

A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a "good machine" simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc. , may be incorporated into the semiconductor substrate.