Scott R Munroe

US Patent:

51326566, Jul 21, 1992

Filed:

Jun 4, 1991

Appl. No.:

7/711115

Inventors:

Scott C. Munroe - Carlisle MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

G11C 1928
H01L 2978

US Classification:

377 60

Abstract:

A charge-coupled device having a charge source and a floating gate input capable of sampling a voltage and converting it to a proportional charge packet, including precharging the floating gate with a quantity of charge proportional to the sampled voltage, and isolating the floating gate such that the proportional charge substantially remains on the floating gate, and a method for doing same.

US Patent:

42989531, Nov 3, 1981

Filed:

Feb 28, 1979

Appl. No.:

6/016334

Inventors:

Scott C. Munroe - Acton MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

G06G 719
H03K 5195

US Classification:

364825

Abstract:

A method and an apparatus for selectively summing the time-varying components of a plurality of electrical voltages are disclosed. The electrical voltages can each be characterized by a quiescent bias component and a time-varying small signal information component. Each electrical voltage is selectively connected to at most one of a plurality of summing buses and each bus is allowed to separately float to a quiescent voltage level corresponding approximately to a selected average value of the bias components of the signals connected thereto. The potential difference measured between the buses corresponds to the difference in the weighted average values of the time-varying components connected to each bus. The weights may be equal or unequal. The method and apparatus provide means for implementing programmable transversal filters and correlation devices.

US Patent:

56708831, Sep 23, 1997

Filed:

Nov 20, 1995

Appl. No.:

8/560650

Inventors:

Geoff O'Donoghue - Andover MA
Scott C. Munroe - Carlisle MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H01H 3102
G01R 3126
H01L 2166

US Classification:

324537

Abstract:

An interlevel conductor defect characterization integrated circuit test structure including first and second spaced test pads, a conductor layer, an insulator layer between the conductor layer and the test pads; and a first interlevel conductor having a unit cross-sectional conductive area extending between the first test pad and the conductor layer, and a second interlevel conductor extending between said second test pad and said conductor layer and having a cross-sectional conductive area substantially greater than the unit area for detecting defects which restrict the current carrying capacity of said unit area of the first interlevel conductor but not the second interlevel conductor.

US Patent:

56712529, Sep 23, 1997

Filed:

Sep 21, 1994

Appl. No.:

8/310050

Inventors:

Janos Kovacs - N. Andover MA
Scott C. Munroe - Carlisle MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04L 2706

US Classification:

375316

Abstract:

A data receiving and processing channel including analog signal processing circuitry operable for receiving data in the form of an input analog signal, and modifying the input signal in accordance with selected parameters so as to generate a modified analog input signal. According to one embodiment, there is provided a charge domain signal equalizer which initially transforms the modified analog input signal into a corresponding analog charge domain signal, the equalizer performing waveform shaping of the analog charge domain signal in accordance with a predetermined signal response template; a charge domain analog-to-digital converter operable for converting the analog charge domain signal into a corresponding digital signal; and a digital signal processor operable for recovering a digital bit stream from the digital signal which is indicative of the original data. In an alternative embodiment, there is provided an analog-to-digital converter operable for converting the modified analog input signal into a corresponding digital signal; a charge signal equalizer which initially transforms the digital signal into a corresponding digital charge signal, the equalizer performing waveform shaping of the digital charge signal in accordance with a predetermined signal response template; and a charge domain digital signal processor operable for recovering a digital bit stream from the digital charge domain signal which is indicative of the original data.

US Patent:

55919960, Jan 7, 1997

Filed:

Mar 24, 1995

Appl. No.:

8/409809

Inventors:

Geoffrey T. Haigh - Boxford MA
Scott C. Munroe - Carlisle MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H01L 27148
H01L 29768

US Classification:

257238

Abstract:

A device for producing an output voltage which is proportional to an applied magnetic field. The device includes a plurality charge injection regions, a corresponding plurality of charge exit regions, and a charge transfer region. The charge transfer region includes gate electrodes which serve to propagate at least one isolated charge packet across the charge transfer region in a predetermined direction from the charge input region to the charge output region. The charge packet is subject to the applied magnetic field which is perpendicular to the charge transfer region so as to induce a resultant potential that is orthogonal to both the applied magnetic field and the predetermined direction. Furthermore, the resultant potential effects a lateral redistribution of charge carriers in the packet. A recirculation configuration allows for a recycling of the packet from the output region back to the input region in order to accommodate a continuation of the redistribution of charge carriers.