Scott Tu Nguyen

US Patent:

8012877, Sep 6, 2011

Filed:

Nov 19, 2008

Appl. No.:

12/273835

Inventors:

Scott Cuong Nguyen - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/302

US Classification:

438689, 438734, 438723, 438738, 438756, 438724, 438743, 438757, 438744

Abstract:

Exemplary embodiments provide a method for fabricating an integrated circuit (IC) device with reduced streak defects. In one embodiment, the IC device structure can be formed having a first pad oxide-based layer on a front side of a semiconductor substrate and having an oxide-nitride-based structure on a backside of the semiconductor substrate. The IC device structure can be etched to remove a nitride-related material from the backside oxide-nitride-based structure, and further to remove the first pad oxide-based layer from the front side of the semiconductor substrate. On the removed front side of the semiconductor substrate a second pad oxide-based layer can be formed, e. g. , for forming an isolation structure for device component or circuitry isolation.

US Patent:

20080076254, Mar 27, 2008

Filed:

Sep 27, 2006

Appl. No.:

11/528255

Inventors:

Scott Cuong Nguyen - Garland TX, US
Keith David Fenstermacher - Murphy TX, US
David Michael Smith - Plano TX, US
Courtney Michael Hazelton - Richardson TX, US

International Classification:

H01L 21/471

US Classification:

438694, 438954, 438786

Abstract:

Yield loss in semiconductor processing is mitigated by forming a resist over an active side of a semiconductor workpiece or wafer, as well as around the edge of the wafer. The resist mitigates the creation of contaminants, such as nitride flakes, for example, that can develop when an oxide, nitride, oxide (ONO) layer is removed from the back or in-active side of the wafer. In the absence of the resist, such flakes may migrate to the front or active side of the wafer and cause defects to form therein, which can result in yield loss.

US Patent:

20120058614, Mar 8, 2012

Filed:

Aug 16, 2011

Appl. No.:

13/211095

Inventors:

Scott Cuong Nguyen - Garland TX, US
Phuong-Lan Thi Tran - Las Colinas TX, US
Michelle Marie Eastlack - Richardson TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - DALLAS TX

International Classification:

H01L 21/336
H01L 21/28

US Classification:

438264, 438664, 257E21422, 257E21158

Abstract:

A process of forming an integrated circuit including an MOS transistor, in which a pre-metal deposition cleanup prior to depositing metal for silicide formation includes an HF etch, a first SC etch, a piranha etch and a second SC etch, so that a native oxide on the source/drain regions is less the 2 nanometers thick before deposition of the silicide metal. A process of forming a metal silicide layer on an integrated circuit containing an MOS transistor, in which a pre-metal deposition cleanup prior to depositing metal for silicide formation includes an HF etch, a first SC etch, a piranha etch and a second SC etch, so that a native oxide on the source/drain regions and the MOS gate is less the 2 nanometers thick before deposition of the silicide metal.