Scott F Nolan

US Patent:

6714553, Mar 30, 2004

Filed:

Apr 15, 1998

Appl. No.:

09/060575

Inventors:

Nigel T. Poole - Natick MA
Scott William Nolan - Milford MA
Barry A. Spinney - Wayland MA
Richard L. Szmauz - New Ipswich NH

Assignee:

Top Layer Networks, Inc. - Westboro MA

International Classification:

H04L 1228

US Classification:

370412, 370419, 710 52

Abstract:

A process and system for flexibly switching connections of data packet flows between nodes of data processing system networks by dividing data packets into cells and logically linking these cells on multiple queues of linked pointer lists.

US Patent:

60441216, Mar 28, 2000

Filed:

Jul 22, 1997

Appl. No.:

8/898148

Inventors:

Scott W. Nolan - Milford MA
Nigel T. Poole - Natick MA
Ronald Salett - Framingham MA

Assignee:

Cabletron Systems, Inc. - Rochester NH

International Classification:

H04L 700

US Classification:

375354

Abstract:

An apparatus and method for receiving time skewed data from a parallel data bus. A data transfer on the parallel data bus is preceded by a start-of-cell delimiter consisting of a predetermined sequence of pulses on each of the data signals. The data is received from the bus by receive logic employing a local clock. Sampling logic is used to sample each of the data signals received from the bus at a rate which is higher than the local clock rate. Sample registers store a plurality of samples of corresponding data signals, the number of samples stored being large enough to store at least some of the pulses constituting the start-of-cell delimiter. Start-of-cell detect and center select logic is used for determining that a start-of-cell delimiter is stored in each of the sample registers, and for determining which of the samples stored in each of the sample registers represents the approximate center sample of one of the pulses of the start-of-cell delimiter. These center samples correspond to the data signals on the bus, but are de-skewed and synchronous with the local clock.

US Patent:

20160132987, May 12, 2016

Filed:

Nov 10, 2014

Appl. No.:

14/537589

Inventors:

- San Diego CA, US
Andrew Evan Gruber - Arlington MA, US
Guofang Jiao - San Diego CA, US
Zhenyu Qi - Auburndale MA, US
Gregory Steve Pitarys - Stow MA, US
Scott William Nolan - Holliston MA, US

International Classification:

G06T 1/20
G09G 5/18

Abstract:

This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.

US Patent:

20150131919, May 14, 2015

Filed:

Nov 8, 2013

Appl. No.:

14/075872

Inventors:

- San Diego CA, US
Ajay NAWANDHAR - Bangalore, IN
Scott William NOLAN - Holliston MA, US
Elina KAMENETSKAYA - Somerville MA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

G06T 1/20
G06T 15/04
G06T 11/00
G06T 9/00

US Classification:

382233

Abstract:

Various apparatuses and methods are disclosed for processing texture data compressed with a first compression algorithm and texture data compressed with a second compression algorithm. A processing system may be used to determine whether the compressed texture data is compressed with the first or second compression algorithm, and process the compressed texture data using a decompression algorithm corresponding to the compression algorithm used to compress the texture date.