Scott F Norton

US Patent:

7516151, Apr 7, 2009

Filed:

Nov 1, 2004

Appl. No.:

10/979413

Inventors:

Scott J. Norton - San Jose CA, US
Hyun J. Kim - Sunnyvale CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 17/00

US Classification:

707102, 707101, 707202

Abstract:

A computer-implemented method for traversing a first set of objects in a first dynamic list in a computer system. The method includes partitioning copies of the first set of objects into a plurality of second dynamic lists, each of the plurality of second dynamic lists being configured to contain a subset of the copies of the first set of objects, copies of the first set of objects being disposed in the plurality of second dynamic lists. The method also includes traversing the plurality of second dynamic lists using a plurality of traversal threads, thereby causing at least some of the copies of the first set of objects to be traversed in parallel.

US Patent:

7698540, Apr 13, 2010

Filed:

Oct 31, 2006

Appl. No.:

11/591140

Inventors:

Scott J. Norton - San Jose CA, US
Thomas L. Vaden - Neshanle Station NJ, US
James Callister - Windsor CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 9/00

US Classification:

712228, 718108, 714 10

Abstract:

In an embodiment of the invention, a method for dynamic hardware multithreading, includes: using a hardware halt function or a hardware yield function in a processor core in order to enable or disable a hardware thread that shares the core; wherein the hardware thread is disabled by placing the hardware thread in a halt state or yield state, and allowing another hardware thread to utilize the core.

US Patent:

7743383, Jun 22, 2010

Filed:

Nov 1, 2004

Appl. No.:

10/979407

Inventors:

Scott J. Norton - San Jose CA, US
Hyun J. Kim - Sunnyvale CA, US
Swapneel Kekre - Sunnyvale CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 9/46

US Classification:

718106, 718105, 718102

Abstract:

A method in a computer system for coordinating scheduling of threads among a plurality of processors. The method includes collecting, using a cooperative scheduling component (CSC), system data pertaining to the plurality of processors. The method further includes calculating, using the CSC, unified scheduling-related parameters (USRPs) from the system data. The method additionally includes furnishing the USRPs from the CSC to at least two of a thread launcher, a thread balancer, and a thread stealer, whereby at least two of the thread launcher, the thread balancer, and the thread stealer employ the USRPs to perform their respective scheduling-related tasks.

US Patent:

7793293, Sep 7, 2010

Filed:

Nov 1, 2004

Appl. No.:

10/979060

Inventors:

Scott J. Norton - San Jose CA, US
Hyun J. Kim - Sunnyvale CA, US
Swapneel Kekre - Sunnyvale CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 9/46

US Classification:

718102, 718105

Abstract:

An arrangement, in a computer system, for coordinating scheduling of threads on a plurality of processor sets (PSETs). The arrangement includes a first processor set (PSET) having a first set of scheduling resources, the first set of scheduling resources. The arrangement further includes a second processor set (PSET) having a second set of scheduling resources. The first set of scheduling resources is configured to schedule threads assigned to the first PSET only among processors of the first PSET, and the second set of scheduling resources is configured to schedule threads assigned to the second PSET only among processors of the second PSET.

US Patent:

8402463, Mar 19, 2013

Filed:

Oct 30, 2006

Appl. No.:

11/554566

Inventors:

Scott J. Norton - San Jose CA, US
Hyun Kim - Sunnyvale CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 9/46
G06F 9/30

US Classification:

718100, 712216

Abstract:

A determination of processor core utilization by a plurality of hardware threads over a time interval is made through a division of a length of the time interval by a total count of the plurality of hardware threads.

US Patent:

20060168254, Jul 27, 2006

Filed:

Nov 1, 2004

Appl. No.:

10/979412

Inventors:

Scott Norton - San Jose CA, US
Hyun Kim - Sunnyvale CA, US
Swapneel Kekre - Sunnyvale CA, US

International Classification:

G06F 15/177
G06F 15/16

US Classification:

709229000, 709220000

Abstract:

An arrangement, in a computer system, for coordinating scheduling of threads on a processor associated with a scheduling-enabled entity. The arrangement includes a policy database of scheduling policies. The arrangement further includes an automatic policy selector associated with the scheduling-enabled entity. The automatic policy selector is configured to automatically select one of the scheduling policies responsive to a triggering event that includes at least one of a first event and a second event. The first event represents a change in configuration of the scheduling-enabled entity and the second event represents a policy selection from a human operator. One of the scheduling policies is employed to schedule the threads on the processors after being selected by the automatic policy selector.

US Patent:

20080184233, Jul 31, 2008

Filed:

Jan 30, 2007

Appl. No.:

11/700748

Inventors:

Scott J. Norton - San Jose CA, US
Hyun Kim - Sunnyvale CA, US

International Classification:

G06F 9/46

US Classification:

718100

Abstract:

In an embodiment of the invention, an apparatus and method to abstract a multithreaded processor core to single threaded processor core include performing the steps of: viewing, by an operating system, a first hardware thread and a second hardware thread in a processor core; and viewing, by a user application, the first hardware thread and the second hardware thread as a single CPU object.

US Patent:

20080271027, Oct 30, 2008

Filed:

Apr 27, 2007

Appl. No.:

11/796511

Inventors:

Scott J. Norton - San Jose CA, US
Hyun Kim - Sunnyvale CA, US

International Classification:

G06F 9/46

US Classification:

718103

Abstract:

An embodiment of the invention provides an apparatus and method for fair share scheduling with hardware multithreading. The apparatus and method include the acts of: executing, by a first hardware thread in a processor core, a first software thread belonging to a fair share group; and permitting a second hardware thread in the processor core to execute a second software thread if that second software thread belongs to the fair share group.