Scott William Rodgers

US Patent:

7430578, Sep 30, 2008

Filed:

Jun 30, 2003

Appl. No.:

10/610831

Inventors:

Eric Debes - Santa Clara CA, US
William W. Macy - Palo Alto CA, US
Jonathan J. Tyler - Austin TX, US
James Coke - Shingle Springs CA, US
Frank Binns - Hillsboro OR, US
Scott Rodgers - Hillsboro OR, US
Peter Ruscito - Folsom CA, US
Bret Toll - Hillsboro OR, US
Vesselin Naydenov - Folsom CA, US
Masood Tahir - Orangevale CA, US
David Jackson - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/38

US Classification:

708603

Abstract:

A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.

US Patent:

7743233, Jun 22, 2010

Filed:

Apr 5, 2005

Appl. No.:

11/100032

Inventors:

Hong Wang - Fremont CA, US
Gautham N. Chinya - Hillsboro OR, US
Richard A. Hankins - San Jose CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
John Shen - San Jose CA, US
Per Hammarlund - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
Jason W. Brandt - Austin TX, US
Prashant Sethi - Folsom CA, US
Douglas M. Carmean - Beaverton OR, US
Baiju V. Patel - Portland OR, US
Scott Dion Rodgers - Hillsboro OR, US
Ryan N. Rakvic - Palo Alto CA, US
John L. Reid - Portland OR, US
David K. Poulsen - Champaign IL, US
Sanjiv M. Shah - Champaign IL, US
James Paul Held - Portland OR, US
James Charles Abel - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/00

US Classification:

712220

Abstract:

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

US Patent:

20070006231, Jan 4, 2007

Filed:

Jun 30, 2005

Appl. No.:

11/173326

Inventors:

Hong Wang - Fremont CA, US
John Shen - San Jose CA, US
Ed Grochowski - San Jose CA, US
James Held - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
Shivnandan Kaushik - Portland OR, US
Gautham Chinya - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
Per Hammarlund - Hillsboro OR, US
Xinmin Tian - Union City CA, US
Anil Aggarwal - Portland OR, US
Scott Rodgers - Hillsboro OR, US
Prashant Sethi - Folsom CA, US
Baiju Patel - Portland OR, US
Richard Hankins - San Jose CA, US

International Classification:

G06F 9/46

US Classification:

718100000

Abstract:

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

US Patent:

20130054940, Feb 28, 2013

Filed:

Sep 10, 2012

Appl. No.:

13/608970

Inventors:

Hong Wang - Fremont CA, US
John Shen - San Jose CA, US
Ed Grochowski - San Jose CA, US
James Paul Held - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
Shivnandan D. Kaushik - Portland OR, US
Gautham Chinya - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
Per Hammarlund - Hillsboro OR, US
Xinmin Tian - Union City CA, US
Anil Aggarwal - Portland OR, US
Scott Dion Rodgers - Hillsboro OR, US
Prashant Sethi - Folsom CA, US
Baiju V. Patel - Portland OR, US
Richard Andrew Hankins - San Jose CA, US

International Classification:

G06F 9/312

US Classification:

712205, 712E09033

Abstract:

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

US Patent:

20130219399, Aug 22, 2013

Filed:

Mar 15, 2013

Appl. No.:

13/843164

Inventors:

Hong Wang - Santa Clara CA, US
John Shen - San Jose CA, US
Edward Grochowski - San Jose CA, US
Richard Hankins - Santa Clara CA, US
Gautham Chinya - Hillsboro OR, US
Bryant Bigbee - Scottsdale AZ, US
Shivnandan Kaushik - Portland OR, US
Xiang Chris Zou - Hillsboro OR, US
Per Hammarlund - Hillsboro OR, US
Scott Dion Rodgers - Hillsboro OR, US
Xinmin Tian - Union City CA, US
Anil Aggawal - Portland OR, US
Prashant Sethi - Folsom CA, US
Baiju Patel - Portland OR, US
James Held - Portland OR, US

International Classification:

G06F 9/48

US Classification:

718102

Abstract:

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

US Patent:

20170010895, Jan 12, 2017

Filed:

Sep 26, 2016

Appl. No.:

15/276290

Inventors:

- Santa Clara CA, US
John P. Shen - San Jose CA, US
Edward T. Grochowski - San Jose CA, US
Richard A. Hankins - San Jose CA, US
Gautham N. Chinya - Hillsboro OR, US
Bryant E. Bigbee - Scottsdale AZ, US
Shivnandan D. Kaushik - Portland OR, US
Xiang Chris Zou - Hillsboro OR, US
Per Hammarlund - Hillsboro OR, US
Scott Dion Rodgers - Hillsboro OR, US
Xinmin Tian - Fremont CA, US
Anil Aggarwal - Portland OR, US
Prashant Sethi - Folsom CA, US
Baiju V. Patel - Portland OR, US
James P. Held - Portland OR, US

International Classification:

G06F 9/38
G06F 9/30
G06F 9/48

Abstract:

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

US Patent:

20160019067, Jan 21, 2016

Filed:

Sep 26, 2015

Appl. No.:

14/866875

Inventors:

Hong Wang - Santa Clara CA, US
John P. Shen - San Jose CA, US
Edward T. Grochowski - San Jose CA, US
Richard A. Hankins - Santa Clara CA, US
Gautham N. Chinya - HILLSBORO OR, US
Bryant E. Bigbee - Scottsdale AZ, US
Shivnandan D. Kaushik - Portland OR, US
Xiang Chris Zou - Beaverton OR, US
Per Hammarlund - Hillsboro OR, US
Scott Dion Rodgers - Hillsboro OR, US
Xinmin Tian - Union City CA, US
Anil Aggawal - Portland OR, US
Prashant Sethi - Folsom CA, US
Baiju V. Patel - Portland OR, US
James P Held - Portland OR, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

US Patent:

20150178078, Jun 25, 2015

Filed:

Dec 21, 2013

Appl. No.:

14/138054

Inventors:

H. Peter Anvin - San Jose CA, US
Scott D. Rodgers - Hillsboro OR, US

International Classification:

G06F 9/30
G06F 9/34

Abstract:

Instructions and logic provide base register swap status verification functionality. Embodiments include a processor having a first model specific register (MSR) to store a first base address corresponding to a segment for a first execution context and a second MSR to store a second base address corresponding to a segment for a second context. A third register stores a base register swap status field corresponding to the segment of the first and second contexts. A decode unit decodes a swap instruction and execution logic executes an exchange of the first MSR value and the second MSR value responsive to the swap instruction. The execution logic determines if said exchange of the first MSR value and the second MSR value completed successfully, and changes a value of the base register swap status field responsive to a determination that said exchange completed successfully.