Scott A Tetreault

US Patent:

6425109, Jul 23, 2002

Filed:

Jul 23, 1999

Appl. No.:

09/360384

Inventors:

Charles N. Choukalos - Burlington VT
Alvar Antonio Dean - Essex Junction VT
Scott Alan Tetreault - Georgia VT
Sebastian Theodore Ventrone - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 1

Abstract:

A system and method for interconnecting a plurality of cores into a single functional core. The method involves creating for each core a pin configuration structure based on a set of configuration rules. When the cores to be interconnected are selected, the pin configuration structure is accessed by the configurator program tool of the present invention. The configurator program tool then connects the cores together using the pin configuration structure and configuration rules for the selected cores. The configurator program tool generates an error-free high level model of the interconnected cores. The configurator program tool allows configuration flexibility and is general enough to handle most configuration scenarios. The tool is also easy to code, extensible, and can be applied to existing core designs with no modification of the cores themselves.

US Patent:

6535016, Mar 18, 2003

Filed:

May 11, 2001

Appl. No.:

09/852784

Inventors:

Charles N. Choukalos - Burlington VT
Alvar A. Dean - Essex junction VT
Scott A. Tetreault - Georgia VT
Sebastian T. Ventrone - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 1900

US Classification:

326 8, 326 38

Abstract:

A method for preventing illicit copying of an application specific integrated circuit (ASIC). The ASIC is defined by a net list which includes a timer circuit for disabling the ASIC. The timer circuit includes a plurality of stages which are distributed in different cores of the ASIC to inhibit detection and removal of the circuit. The timer times out after a period which is set to permit evaluation of the ASIC design. Following the time out period, further use of the ASIC design is inhibited.

US Patent:

6711719, Mar 23, 2004

Filed:

Aug 13, 2001

Appl. No.:

09/928573

Inventors:

John Maxwell Cohn - Richmond VT
Alvar A. Dean - Groton MA
Amir H. Farrahi - Peekskill NY
David J. Hathaway - Underhill Center VT
Thomas Michael Lepsic - Jeffersonville VT
Patrick Edward Perry - Shelburne VT
Scott A. Tetreault - Clinton MA
Sebastian T. Ventrone - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 2, 716 4, 716 7, 716 10

Abstract:

In integrated circuit (IC) designs, a component of power consumed may be represented as Power=Â FCV , where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.

US Patent:

6792582, Sep 14, 2004

Filed:

Nov 15, 2000

Appl. No.:

09/713829

Inventors:

John M Cohn - Essex Junction VT
Alvar A. Dean - Groton MA
David J. Hathaway - Underhill Center VT
David E. Lackey - Jericho VT
Thomas M. Lepsic - Jeffersonville VT
Susan K. Lichtensteiger - Essex Junction VT
Scott A. Tetreault - Franklin VT
Sebastian T. Ventrone - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 7, 716 2, 716 4, 716 9, 326 38

Abstract:

Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into âbinsâ, which are areas of the design. In this way, a semiconductor chip design may be âslicedâ into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.

US Patent:

6970814, Nov 29, 2005

Filed:

Mar 30, 2000

Appl. No.:

09/539020

Inventors:

Carl L. Ashley - Essex Junction VT, US
Charles N. Choukalos - Burlington VT, US
Scott A. Tetreault - Georgia VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F017/50

US Classification:

703 14, 703 15, 703 20, 716 1, 716 2, 716 3, 716 4, 716 17, 716 18

Abstract:

A method and structure for simulating a circuit comprising inputting, from a customer site, initial memory states, and initial input signals to core logic within a host site, simulating the circuit utilizing the host site and the customer site connected though a wide area network (wherein the host site contains the core logic and the customer site contains customer logic, the core logic and the customer logic forming the circuit), comparing test output signals with the desired output signals, and altering the customer logic until the test output signals are consistent with the desired output signals.

US Patent:

6985004, Jan 10, 2006

Filed:

Feb 12, 2001

Appl. No.:

09/781369

Inventors:

John M. Cohn - Richmond VT, US
Alvar A. Dean - Groton MA, US
Amir H. Farrahi - Peekskill NY, US
David J. Hathaway - Underhill Center VT, US
Thomas M. Lepsic - Jeffersonville VT, US
Jagannathan Narasimhan - Millwood NY, US
Scott A. Tetreault - Georgia VT, US
Sebastian T. Ventrone - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 17/16

US Classification:

326 21, 326 26, 333 12

Abstract:

An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

US Patent:

7346875, Mar 18, 2008

Filed:

Jul 7, 2005

Appl. No.:

11/176712

Inventors:

John M. Cohn - Richmond VT, US
Alvar A. Dean - Groton MA, US
Amir H. Farrahi - Peekskill NY, US
David J. Hathaway - Underhill Center VT, US
Thomas M. Lepsic - Jeffersonville VT, US
Jagannathan Narasimhan - Millwood NY, US
Scott A. Tetreault - Marlborough MA, US
Sebastian T. Ventrone - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 6, 716 2, 716 10, 716 13

Abstract:

An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

US Patent:

7469395, Dec 23, 2008

Filed:

Dec 7, 2007

Appl. No.:

11/952544

Inventors:

John M. Cohn - Richmond VT, US
Alvar A. Dean - Groton MA, US
Amir H. Farrahi - Peekskill NY, US
David J. Hathaway - Underhill Center VT, US
Thomas M. Lepsic - Jeffersonville VT, US
Jagannathan Narasimhan - Millwood NY, US
Scott A. Tetreault - Marlborough MA, US
Sebastian T. Ventrone - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 6, 716 2, 716 10, 716 13

Abstract:

An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φper clock cycle that is no less than a pre-selected minimum same-direction switching probability φor has an opposite-direction switching probability φper clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φ. The first wire and the second wire satisfies at least one mathematical relationship involving Land Wwhere Wis defined as a spacing between the first wire and the second wire, and Lis defined as a common run length of the first wire and the second wire.