Seah Sun Too from 27333 SE 10Th Ct, Redmond, WA 98075, age 59

Us Patents

Semiconductor Component And Method Of Manufacture
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US Patent:

6936501, Aug 30, 2005
Filed:

Apr 5, 2004
Appl. No.:

10/818981
Inventors:

Seah Sun Too - San Jose CA, US
James Hayward - Santa Clara CA, US
Janet D. Kirkland - Fremont CA, US
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H01L023/12
US Classification:

438122, 438106, 257704, 257706, 257713, 257724
Abstract:

A semiconductor component having a lid for protecting a semiconductor chip and a method for manufacturing the semiconductor component. The semiconductor chip has an active surface and a mounting surface. It is flip-chip mounted to a support substrate so the active surface is adjacent the support substrate. A passive or active circuit element may be mounted to the support substrate. The mounting surface of the semiconductor chip has a radius of curvature. A thermal interface material is dispensed on the mounting surface of the semiconductor chip. A lid is coupled to the support substrate via a lid adhesive. A portion of the lid has a radius of curvature that corresponds to the radius of curvature of the semiconductor chip. A force is applied to the lid so that it contacts the thermal interface material and urges the interface material to the sides of the semiconductor chip. The force causes wetting of the thermal interface material.

Methods And Fixture For Coupling A Lid To A Support Substrate
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US Patent:

7256065, Aug 14, 2007
Filed:

Jun 3, 2004
Appl. No.:

10/859673
Inventors:

Seah Sun Too - San Jose CA, US
Edward Alcid - Sunnyvale CA, US
Ahmad Juwanda - Bayan Lepas Penang, MY
Keng Sang Cha - Kumbar Penang, MY
Leang Hua Kam - Georgetown Penang, MY
Tek Seng Tan - Bayan Lepas Penang, MY
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H01L 21/00
US Classification:

438106, 438118
Abstract:

A method for coupling a lid to a support substrate having a semiconductor chip coupled thereto and a clamp fixture. Each semiconductor component has a semiconductor chip mounted to a semiconductor component and a lid coupled to the support substrate via a lid attach material. The lid attach material is cured either using a two-step process that includes a partial cure step followed by a clampless cure step or by curing the die attach material in a clamp fixture without including a pre-cure step. The semiconductor component manufacture decides on the curing approach based on cost and the number of semiconductor components being manufactured. If the semiconductor manufacturer opts for curing with a clamp fixture, the clamp fixture includes a base plate insert on which the semiconductor components are placed and a compression mechanism that includes a compression plate having a compressive material disposed thereon.

Lga Fixture For Indium Assembly Process
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US Patent:

7256067, Aug 14, 2007
Filed:

May 1, 2006
Appl. No.:

11/381089
Inventors:

Seah Sun Too - San Jose CA, US
Tek Seng Tan - Panang, MY
Keng Sang Cha - Penang, MY
Kee Hean Keok - Perak, MY
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H01L 21/00
US Classification:

438106, 438108, 438455, 438117, 438122, 257704, 257710, 257E2318, 257E215
Abstract:

An integrated circuit lid fixture and methods of using the same are provided. In one aspect, an integrated circuit lid fixture is provided that includes a base that has a plurality of pillars. Each of the plurality of pillars has a surface for supporting a substrate that may be removably seated thereon. The surfaces of the plurality of pillars have a first footprint at least as large as a footprint of the substrates to be placed thereon. A plate is provided for applying a compressive force to an integrated circuit lid positioned on any of the substrates removably seated on the pillars.

Method Of Integrated Circuit Packaging
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US Patent:

7513035, Apr 7, 2009
Filed:

Jun 7, 2006
Appl. No.:

11/422807
Inventors:

Seah Sun Too - San Jose CA, US
Mohammad Khan - San Jose CA, US
James Hayward - Santa Clara CA, US
Jacquana Diep - San Jose CA, US
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H05K 3/30
H05K 3/34
US Classification:

29832, 29825, 29833, 29840, 438121
Abstract:

Various integrated circuit package elements are provided. In one aspect, an integrated circuit package device is provided that includes a lid for covering an integrated circuit. The lid has a convex surface for applying pressure on the integrated circuit when the lid is placed in a selected position. In another aspect, an integrated circuit package device is provided that includes a lid that has a surface for applying pressure to an integrated circuit when the lid is in a selected position. A gold film is coupled to the surface. The gold film has a periphery and a plurality of rounds extending from the periphery.

Reduction Of Damage To Thermal Interface Material Due To Asymmetrical Load
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US Patent:

7544542, Jun 9, 2009
Filed:

Aug 7, 2006
Appl. No.:

11/462993
Inventors:

Seah Sun Too - San Jose CA, US
Raj N. Master - San Jose CA, US
Jacquana Diep - San Jose CA, US
Mohammad Khan - Santa Clara CA, US
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H01L 21/44
US Classification:

438125, 257E23087, 257E2309, 257E23092, 257E25013
Abstract:

Various method and apparatus for packaging an integrated circuit are provided. In one aspect, a method of packaging an integrated circuit is provided that includes coupling an integrated circuit to a substrate, mixing an adhesive with a plurality of particles, and coupling a lid to the substrate with the adhesive. At least a portion of the plurality of particles in the adhesive oppose compressive force from the lid to restrict rotation of the lid relative to the substrate.

Integrated Circuit Package Lid With A Wetting Film
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US Patent:

7633151, Dec 15, 2009
Filed:

Mar 16, 2007
Appl. No.:

11/687514
Inventors:

Seah Sun Too - San Jose CA, US
Jacquana Diep - San Jose CA, US
Mohammad Khan - San Jose CA, US
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H01L 23/04
H01L 23/12
H01L 23/49
H01L 21/58
H01L 21/44
US Classification:

257704, 257E23003, 257E23024, 257E23188, 257E21502, 257E21505, 257E23193, 257E23104, 257E2309, 257E23087, 257 23092, 257E25013, 257711, 438126, 438118, 438125
Abstract:

Various integrated circuit packages, lids therefor and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing an integrated circuit package lid that has a surface adapted to face towards an integrated circuit, and forming a wetting film on the surface. The wetting film has at least one void where the surface of the lid is exposed. The void inhibits bonding so that a stress reduction site is produced.

Void Reduction In Indium Thermal Interface Material
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US Patent:

7651938, Jan 26, 2010
Filed:

Jun 7, 2006
Appl. No.:

11/422795
Inventors:

Seah Sun Too - San Jose CA, US
Hsiang Wan Liau - Penang, MY
Janet Kirkland - Fremont CA, US
Tek Seng Tan - Penang, MY
Raj N. Master - San Jose CA, US
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H01L 21/44
H01L 23/12
US Classification:

438615, 438612, 438108, 257704, 257779, 257778, 257E23109
Abstract:

Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.

Lid Attachment Mechanism
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US Patent:

7860599, Dec 28, 2010
Filed:

Mar 29, 2007
Appl. No.:

11/693156
Inventors:

Seah Sun Too - San Jose CA, US
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

G06F 19/00
US Classification:

700121
Abstract:

Apparatus and methods for assembling semiconductor chips packages are provided. In one aspect, a method of manufacturing is provided that includes placing a first set of semiconductor chip package substrates in a first group of receptacles of a first processing station. Each of the first set of semiconductor chip package substrates has a first footprint. The receptacles of the first group being dimensioned to accommodate the first footprint. A second set of semiconductor chip package substrates is placed in a second group of receptacles of the first processing station. Each of the second set of semiconductor chip package substrates has a second footprint larger than the first footprint. The receptacles of the second group being dimensioned to accommodate the second footprint. A first set of lids is placed on the first set of semiconductor chip package substrates and a second group of lids is placed on the second set of semiconductor chip package substrates.