Sean M Fitzpatrick

US Patent:

6624678, Sep 23, 2003

Filed:

Oct 9, 2002

Appl. No.:

10/267796

Inventors:

Frederic Boutaud - Belmont MA
Sean M. FitzPatrick - Westford MA
Paul D. Krivacek - Winchester MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03K 3037

US Classification:

327206

Abstract:

Described is a Schmitt trigger cell that can be disabled under conditions of unknown gate voltages (e. g. , floating or toggling input) such that the core is isolated from the Schmitt trigger input. This is accomplished by circuitry that disables current flow through those transistors whose gate voltages are unknown during such conditions and that forces a known output onto the output terminal.

US Patent:

6624682, Sep 23, 2003

Filed:

Oct 9, 2002

Appl. No.:

10/267563

Inventors:

Frederic Boutaud - Belmont MA
Sean M. FitzPatrick - Westford MA
Paul D. Krivacek - Winchester MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03K 508

US Classification:

327310, 327376

Abstract:

Described is an apparatus and a method for pulling an integrated circuit I/O pad to a known state and providing a current path between the pad and a source of potential during periods when an I/O voltage is likely to be floating. At least one I/O transistor coupled between the I/O pad and a source of potential is provided. Also provided is a combinatorial circuit connected to the I/O transistor to turn on the I/O transistor during periods that the I/O voltage is likely to be floating.

US Patent:

20130117582, May 9, 2013

Filed:

May 18, 2012

Appl. No.:

13/474719

Inventors:

Anand Satyamoorthy - Somerville MA, US
Sean Fitzpatrick - Carlisle MA, US

International Classification:

G06F 1/26

US Classification:

713300

Abstract:

The subject matter of this application is embodied in an apparatus that includes a data processor, and a hardware monitor. The hardware monitor can be configured to emulate a critical path of the data processor, measure a parameter associated with the emulated critical path, process the measurement value, and generate an interrupt signal if the processing result meets a criterion. The apparatus also includes a power supply to provide power to the data processor and the hardware monitor, and a controller to control the power supply to adjust an output voltage level of the power supply. The controller upon receiving an interrupt signal from the hardware monitor queries the hardware monitor to obtain a measurement of the parameter and controls the power supply to adjust the output voltage level according to the measurement value.

US Patent:

20130117589, May 9, 2013

Filed:

May 18, 2012

Appl. No.:

13/474716

Inventors:

Anand Satyamoorthy - Somerville MA, US
José Barreiro da Silva - Woburn MA, US
Sean Fitzpatrick - Carlisle MA, US

International Classification:

G06F 1/26
G06F 1/32

US Classification:

713320, 713300

Abstract:

The subject matter of this application is embodied in an apparatus that includes a data processor, and a hardware monitor to emulate a critical path of the data processor and measure a parameter associated with the emulated critical path, process the measurement value, and generate an interrupt signal if the processing result meets a criterion. The apparatus also includes a power supply to provide power to the data processor and the hardware monitor, and a controller to receive the interrupt signal from the hardware monitor and in response to the interrupt signal, controls the power supply to adjust an output voltage level of the power supply.

US Patent:

20130311792, Nov 21, 2013

Filed:

May 18, 2012

Appl. No.:

13/474718

Inventors:

Prahallada Ponnathota - Winchester MA, US
Sean Fitzpatrick - Carlisle MA, US

International Classification:

G06F 1/26
G05F 1/10

US Classification:

713300, 323282

Abstract:

The subject matter of this application is embodied in an apparatus that includes a data processor, and at least one hardware monitor to measure circuit delays associated with the data processor and a power supply to provide power to the data processor. The apparatus also includes a voltage regulator to regulate a voltage level provided by the power supply, and a look-up table having target voltage values and target circuit delay values each corresponding to one or more conditions. The apparatus further includes a controller to control the voltage regulator. The controller at various time points controls the voltage regulator based on target voltage values obtained from the look-up table. In between the time points, the controller controls the voltage regulator based on differences between target circuit delay values and measured circuit delay values.

US Patent:

20130311799, Nov 21, 2013

Filed:

May 18, 2012

Appl. No.:

13/474720

Inventors:

Sean Fitzpatrick - Carlisle MA, US
Anand Satyamoorthy - Somerville MA, US

International Classification:

G06F 1/26
G01R 19/00
G04F 13/00
G01K 13/00
G06F 1/32
G06F 15/00

US Classification:

713320, 713300, 702186, 702178, 702130, 702 64

Abstract:

The subject matter of this application is embodied in an apparatus that includes a data processor, and two or more hardware monitors to measure parameters associated with the data processor. The apparatus also features a power supply to provide power to the data processor and the hardware monitors, and a controller to control the power supply to adjust an output voltage level of the power supply according to measurements from the hardware monitors. Different weight values are applied to the hardware monitors under different conditions, and the power supply output voltage level is controlled according to weighted measurements or values derived from the weighted measurements.