Sean E Kelly

US Patent:

7366998, Apr 29, 2008

Filed:

Nov 8, 2005

Appl. No.:

11/268832

Inventors:

Sean A. Kelly - Boulder CO, US
Roger B. Milne - Boulder CO, US
Jonathan B. Ballagh - Boulder CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 3, 716 4

Abstract:

A method communicates data with efficient conversion between representations in a high-level modeling system. The data is communicated from a first block in a first external format and the data is communicated to a second block in a second external format. The first block has a first internal representation of the data and the second block has a second internal representation of the data. The first internal representation is converted to the second internal representation without intermediate representation in the first and second external formats in response to different first and second external formats or different first and second internal representations. Conversion between the representations of the data is bypassed in response to like first and second external formats and like first and second internal representations. A signal instance is created that communicates the data between the blocks. Converters between data representations are installed in the signal instance on demand.

US Patent:

7386814, Jun 10, 2008

Filed:

Feb 10, 2005

Appl. No.:

11/054864

Inventors:

Jeffrey D. Stroomer - Lafayette CO, US
Roger B. Milne - Boulder CO, US
Isaac W. Foraker - Longmont CO, US
Sean A. Kelly - Boulder CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 3, 716 2, 703 14, 703 15, 703 16

Abstract:

Translation of high-level design blocks into a design specification in a hardware description language (HDL). Each block in the high-level design is assigned to a group. A set of attributes is identical between the blocks in a group. For each group of blocks, a respective set of parameters having different values on subblocks of at least two blocks in the group is determined. An HDL specification is generated for each group. The HDL specification for a group has for each parameter in the set of parameters, a parameter input.

US Patent:

7444603, Oct 28, 2008

Filed:

Dec 15, 2006

Appl. No.:

11/639547

Inventors:

Sean A. Kelly - Boulder CO, US
Roger B. Milne - Boulder CO, US
Jeffrey D. Stroomer - Lafayette CO, US
Jonathan B. Ballagh - Boulder CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 3, 716 2

Abstract:

Methods and apparatus are provided for processing an electronic design in a high level modeling system. A first graph is generated, with the nodes representing basic elements of the electronic design and including a shared node representing the basic element of a block, a port, or a network of the electronic design. Multiple second graphs are generated modeling different aspects of the electronic design. A first and second member of the nodes and edges of respective ones of the second graphs are each associated with the shared node of the first graph. The different aspects of the electronic design of the second-type graphs transformed, with a first attribute of one of the second graphs written to the shared node using the first member, and a second attribute of another of the second graphs determined as a function of the first attribute read from the shared node using the second member.

US Patent:

7669191, Feb 23, 2010

Filed:

Jun 14, 2005

Appl. No.:

11/152631

Inventors:

Sean A. Kelly - Boulder CO, US
Roger B. Milne - Boulder CO, US
Alexander R. Vogenthaler - Boulder CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 9/45
G06F 9/44

US Classification:

717140, 717148, 717150

Abstract:

Implementing a type-safe heterogeneous containers in a memory arrangement of a computing system. In one embodiment, a main object of a class is specified in program source code. The class has a variant type, and the variant type provides at least two different data types, at least one of which is a linear array of objects of one of the data types. The class includes methods for putting and getting a variant object of the variant type in and from the main object. An application of a visitor method, which includes a respective operator for each of the different data types, is specified in the program source code for each method for getting a variant object from the main object. Compilation of the source code results in code that executes the one of the operators corresponding to the data type of a referenced variant object of the main object.

US Patent:

7685541, Mar 23, 2010

Filed:

May 1, 2008

Appl. No.:

12/113231

Inventors:

Jeffrey D. Stroomer - Lafayette CO, US
Roger B. Milne - Boulder CO, US
Isaac W. Foraker - Longmont CO, US
Sean A. Kelly - Boulder CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 3, 716 2, 716 18, 703 14, 703 15, 703 16

Abstract:

Translation of high-level design blocks into a design specification in a hardware description language (HDL). Each block in the high-level design is assigned to a group. A set of attributes is identical between the blocks in a group. For each group of blocks, a respective set of parameters having different values on subblocks of at least two blocks in the group is determined. An HDL specification is generated for each group. The HDL specification for a group has for each parameter in the set of parameters, a parameter input.

US Patent:

7685554, Mar 23, 2010

Filed:

Jul 20, 2005

Appl. No.:

11/185125

Inventors:

Sean A. Kelly - Boulder CO, US
Roger B. Milne - Boulder CO, US
Jeffrey D. Stroomer - Lafayette CO, US
Sreekanth Juttu - Longmont CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 17, 716 3, 716 4, 716 5, 716 16, 716 18, 703 13, 703 14, 703 22

Abstract:

Determining data rates and data types in a an electronic design. In one embodiment, an electronic design is created in a memory arrangement in response to user input. The electronic design includes a plurality of functional blocks and a plurality of nets connecting the functional blocks. In response to user input, an output data rate and an output data type of data output from at least one of the functional blocks are determined. The input data rate and input data type to each functional block coupled via a net to the at least one functional block are equal to the output data rate and output data type, respectively, from the at least one functional block. For each functional block, an output data rate and output data type are determined as a function of the input data rate and the input data type of the functional block.

US Patent:

7797677, Sep 14, 2010

Filed:

Nov 8, 2005

Appl. No.:

11/268801

Inventors:

Jonathan B. Ballagh - Boulder CO, US
Sean A. Kelly - Boulder CO, US
Roger B. Milne - Boulder CO, US
Shay Ping Seng - San Jose CA, US
Jeffrey D. Stroomer - Lafayette CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 9/44

US Classification:

717115, 703 14, 703 15, 703 16, 716 4, 716 5, 716 6, 716 11, 716 12, 716 13, 716 14, 716 15, 716 16

Abstract:

A method of passing data among modules of a heterogeneous software system can include identifying a scripted function to be executed within the heterogeneous software system and building a wrapper script by embedding a call to the scripted function and an XTable object associated with the scripted function within the wrapper script. The method further can include executing the wrapper script thereby causing the scripted function to execute and receiving a result from execution of the scripted function.

US Patent:

7870522, Jan 11, 2011

Filed:

Mar 6, 2008

Appl. No.:

12/043284

Inventors:

Sean A. Kelly - Boulder CO, US
Roger B. Milne - Boulder CO, US
Jonathan B. Ballagh - Boulder CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 4, 716 3, 716 5

Abstract:

A method communicates data with efficient conversion between representations in a high-level modeling system. The data is communicated from a first block in a first external format and the data is communicated to a second block in a second external format. The first block has a first internal representation of the data and the second block has a second internal representation of the data. The first internal representation is converted to the second internal representation without intermediate representation in the first and second external formats in response to different first and second external formats or different first and second internal representations. Conversion between the representations of the data is bypassed in response to like first and second external formats and like first and second internal representations. A signal instance is created that communicates the data between the blocks. Converters between data representations are installed in the signal instance on demand.