Seo Young Kim

US Patent:

20220359115, Nov 10, 2022

Filed:

Jul 26, 2022

Appl. No.:

17/873509

Inventors:

- Santa Clara CA, US
Rahul JAIN - Gilbert AZ, US
Sai VADLAMANI - Chandler AZ, US
Cheng XU - Chandler AZ, US
Ji Yong PARK - Chandler AZ, US
Junnan ZHAO - Gilbert AZ, US
Seo Young KIM - Chandler AZ, US

International Classification:

H01F 27/32
H01L 23/498
H01F 41/04
H01L 21/48
H01F 27/28

Abstract:

Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

US Patent:

20220328431, Oct 13, 2022

Filed:

Jun 28, 2022

Appl. No.:

17/852003

Inventors:

- Santa Clara CA, US
Junnan ZHAO - Gilbert AZ, US
Rahul JAIN - Gilbert AZ, US
Ji Yong PARK - Chandler AZ, US
Sai VADLAMANI - Gilbert AZ, US
Seo Young KIM - Chandler AZ, US

International Classification:

H01L 23/64
H01L 23/498
H01L 23/00
H01L 21/48

Abstract:

Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

US Patent:

20220367104, Nov 17, 2022

Filed:

Jul 26, 2022

Appl. No.:

17/873518

Inventors:

- Santa Clara CA, US
Junnan ZHAO - Gilbert AZ, US
Rahul JAIN - Gilbert AZ, US
Ji Yong PARK - Chandler AZ, US
Sai VADLAMANI - Chandler AZ, US
Seo Young KIM - Chandler AZ, US

International Classification:

H01F 27/28
H01F 27/02
H01F 27/24

Abstract:

Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

US Patent:

20200251467, Aug 6, 2020

Filed:

Apr 22, 2020

Appl. No.:

16/855376

Inventors:

- Santa Clara CA, US
Rahul Jain - Gilbert AZ, US
Seo Young Kim - Chandler AZ, US
Kyu Oh Lee - Chandler AZ, US
Ji Yong Park - Chandler AZ, US
Sai Vadlamani - Chandler AZ, US
Junnan Zhao - Gilbert AZ, US

International Classification:

H01L 27/07
H01L 49/02
H01L 23/64
H01L 23/522
H01L 23/00

Abstract:

Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

US Patent:

20200005994, Jan 2, 2020

Filed:

Jun 27, 2018

Appl. No.:

16/020035

Inventors:

Rahul JAIN - Gilbert AZ, US
Sai VADLAMANI - Chandler AZ, US
Cheng XU - Chandler AZ, US
Ji Yong PARK - Chandler AZ, US
Junnan ZHAO - Gilbert AZ, US
Seo Young KIM - Chandler AZ, US

International Classification:

H01F 27/32
H01F 27/28
H01L 23/498
H01F 41/04
H01L 21/48

Abstract:

Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

US Patent:

20190393217, Dec 26, 2019

Filed:

May 3, 2019

Appl. No.:

16/402588

Inventors:

- Santa Clara CA, US
Rahul Jain - Gilbert AZ, US
Seo Young Kim - Chandler AZ, US
Kyu Oh Lee - Chandler AZ, US
Ji Yong Park - Chandler AZ, US
Sai Vadlamani - Chandler AZ, US
Junnan Zhao - Gilbert AZ, US

International Classification:

H01L 27/07
H01L 49/02
H01L 23/64
H01L 23/522
H01L 23/00

Abstract:

Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

US Patent:

20190355675, Nov 21, 2019

Filed:

May 17, 2018

Appl. No.:

15/982652

Inventors:

- Santa Clara CA, US
Sai VADLAMANI - Chandler AZ, US
Rahul JAIN - Gilbert AZ, US
Junnan ZHAO - Gilbert AZ, US
Ji Yong PARK - Chandler AZ, US
Cheng XU - Chandler AZ, US
Seo Young KIM - Chandler AZ, US

International Classification:

H01L 23/64
H01L 23/498
H01L 21/48
H01L 23/00
H01F 1/12
H01F 41/14

Abstract:

Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.

US Patent:

20190304661, Oct 3, 2019

Filed:

Mar 28, 2018

Appl. No.:

15/938119

Inventors:

- Santa Clara CA, US
Junnan Zhao - Gilbert AZ, US
Rahul Jain - Gilbert AZ, US
Ji Yong Park - Chandler AZ, US
Sai Vadlamani - Chandler AZ, US
Seo Young Kim - Chandler AZ, US

International Classification:

H01F 27/28
H01F 27/24
H01F 27/02

Abstract:

Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.