Seongwoo D Kim from 18221 SW Santoro Dr, Beaverton, OR 97007, age 52, Phone: 5038065302

Soc Architect

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Location:

19750 northwest Phillips Rd, Hillsboro, OR 97124

Industry:

Semiconductors

Work:

Intel Corporation since Jan 2002
Microprocessor Design Engineer

Education:

Iowa State University 1997 - 2001
PhD, Computer Engineering University of Washington 1996 - 1997
PhD, EE University of Washington 1995 - 1996
MS, EE Kwangwoon University 1991 - 1995
BE, Computer Engineering

Skills:

Computer Architecture
Microarchitecture
Processors
Rtl Design
Performance Analysis
Debugging
Asic
Intel
Fpga
Verilog
Microprocessors
Soc
Hardware Architecture
X86
Logic Design
High Performance Computing
Vlsi
Semiconductors
Algorithms
Systemverilog
Functional Verification

Seongwoo Kim

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Seongwoo Kim

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Us Patents

Mechanisms For Utilizing Efficiency Metrics To Control Embedded Dynamic Random Access Memory Power States On A Semiconductor Integrated Circuit Package
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US Patent:

8611170, Dec 17, 2013
Filed:

Dec 30, 2011
Appl. No.:

13/341868
Inventors:

Timothy Y. Kam - Portland OR, US
Jay D. Schwartz - Aloha OR, US
Seongwoo Kim - Beaverton OR, US
Stephen H. Gunther - Beaverton OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 5/14
US Classification:

365226, 365102, 365 94, 365149, 365150, 36518917, 365191, 365227, 36523006, 36523313
Abstract:

Power management of an embedded dynamic random access memory (eDRAM) using collected performance counter statistics to generating a set of one or more eDRAM effectiveness predictions. Using a set of one or more eDRAM effectiveness thresholds, each corresponding to one of the set of eDRAM effectiveness predictions, to determine whether at least one eDRAM effectiveness prediction has crossed over threshold. In the case that at least one eDRAM effectiveness prediction has crossed over its threshold, transitioning the eDRAM to a new power state. Power management is achieved by transitioning to a power-off state or self-refresh state and reducing the amount of power consumed by the eDRAM as compared to a power-on state.

Mechanisms For Enabling Power Management Of Embedded Dynamic Random Access Memory On A Semiconductor Integrated Circuit Package
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US Patent:

20120166822, Jun 28, 2012
Filed:

Dec 30, 2011
Appl. No.:

13/341864
Inventors:

TIMOTHY Y. KAM - Portland OR, US
JAY D. SCHWARTZ - Aloha OR, US
SEONGWOO KIM - Beaverton OR, US
STEPHEN H. GUNTHER - Beaverton OR, US
International Classification:

G06F 1/26
US Classification:

713300
Abstract:

Power management of an embedded dynamic random access memory (eDRAM) by receiving an eDRAM power state transition event and determining both the current power state of the eDRAM and the next power state of the eDRAM from the power states of: a power-on state, a power-off state, and a self-refresh state. Using the current power state and the next power state to determine whether a power state transition is required, and, in the case that a power state transition is required, transition the eDRAM to the next power state. Power management is achieved because transitioning to a power-off state or self-refresh state reduces the amount of power consumed by the eDRAM as compared to the power-on state.

Method, Apparatus, And System For Energy Efficiency And Energy Conservation Including Balancing Power Among Multi-Frequency Domains Of A Processor Based On Efficiency Rating Scheme
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US Patent:

20120173895, Jul 5, 2012
Filed:

Dec 5, 2011
Appl. No.:

13/311467
Inventors:

Seongwoo Kim - Beaverton OR, US
Jeremy Shrall - Portland OR, US
Jay D. Schwartz - Aloha OR, US
Stephen H. Gunther - Beaverton OR, US
Travis C. Furrer - Hillsboro OR, US
International Classification:

G06F 1/00
US Classification:

713300
Abstract:

The efficiency rating (ER) of each domain, in a processor, may be compared and then the power budget may be allocated, effectively, among the domains based on the ERs of the domains. The ER may indicate relative advantage among domains in terms of performance return for a given power budget, i.e., a higher effectiveness may be expected in power utilization if the ER is higher for a domain. The ER of a domain may be defined as (scalability factor/cost factor*alpha). The scalability factor may be defined as a performance increase (in %) brought about by an increase in the clock frequency (in %) provided to the domain. The cost factor may be defined as a power budget value required in bringing about an increase in the clock frequency provided to the domain and alpha is an adjustment factor.