Seung D Rim from 1375 Phelps Ave, San Jose, CA 95117, age 96, Phone: 4086159194

Resumes

Display Electrical Engineer

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Location:

San Francisco, CA

Industry:

Consumer Electronics

Work:

Apple
Display Electrical Engineer
Sunpower Corporation Sep 2009 - Sep 2018
Principal Engineer
Sunpower Corporation Apr 2012 - May 2015
R and D Engineer, Senior Staff
Sunpower Corporation Sep 2009 - Mar 2012
R and D Engineer, Staff
Stanford University 2004 - Aug 2009
Research Assistant

Education:

Stanford University 2004 - 2008
Doctorates, Doctor of Philosophy, Electrical Engineering Stanford University 2002 - 2004
Master of Science, Masters, Electrical Engineering Seoul National University 1995 - 1999
Bachelors, Bachelor of Science, Electrical Engineering Hansung Science High School 1992 - 1995

Skills:

Thin Films
Semiconductors
Semiconductor Device
Simulations
Photovoltaics
Matlab
Nanotechnology
R&D
Process Integration
Optics
C++
Characterization
Design of Experiments
C
Labview
Statistical Data Analysis
Optoelectronics
Python
Failure Analysis
Computational Modeling
Sql
Jmp
Sqlite
Comsol
Code V
Spice

Certifications:

Edx Honor Code Certificate For Energy 101 (Link)
Edx Honor Code Certificate For Principles of Economics With Calculus (Link)

Us Patents

Thin Silicon Solar Cell And Method Of Manufacture
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US Patent:

8486746, Jul 16, 2013
Filed:

Mar 29, 2011
Appl. No.:

13/074350
Inventors:

Seung Bum Rim - Palo Alto CA, US
Michael Morse - San Jose CA, US
Taeseok Kim - San Jose CA, US
Michael J. Cudzinovic - Sunnyvale CA, US
Assignee:

SunPower Corporation - San Jose CA
International Classification:

H01L 21/00
US Classification:

438 57, 438 73, 136252, 136256
Abstract:

A method of fabricating a solar cell is disclosed. The method includes the steps of forming a sacrificial layer on a silicon substrate, forming a doped silicon layer atop the sacrificial substrate, forming a silicon film atop the doped silicon layer, forming a plurality of interdigitated contacts on the silicon film, contacting each of the plurality of interdigitated contacts with a metal contact, and removing the sacrificial layer.

Bypass Diode For A Solar Cell
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US Patent:

8580599, Nov 12, 2013
Filed:

Feb 10, 2012
Appl. No.:

13/371241
Inventors:

Seung Bum Rim - Palo Alto CA, US
Taeseok Kim - San Jose CA, US
David D. Smith - Campbell CA, US
Peter J. Cousins - Menlo Park CA, US
Assignee:

SunPower Corporation - San Jose CA
International Classification:

H01L 21/02
US Classification:

438 59, 438 66, 438 73, 438 98, 438751, 257E27123, 257E27133, 257E31038
Abstract:

Methods of fabricating bypass diodes for solar cells are described. In one embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed on the first conductive region. In another embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed within, and surrounded by, an uppermost portion of the first conductive region but is not formed in a lowermost portion of the first conductive region.

Hybrid Polysilicon Heterojunction Back Contact Cell
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US Patent:

8597970, Dec 3, 2013
Filed:

Dec 21, 2011
Appl. No.:

13/333904
Inventors:

Peter J. Cousins - Menlo Park CA, US
David D. Smith - Campbell CA, US
Seung B. Rim - Palo Alto CA, US
Assignee:

SunPower Corporation - San Jose CA
International Classification:

H01L 31/18
US Classification:

438 71, 257E3113
Abstract:

A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.

Bypass Diode For A Solar Cell
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US Patent:

20110284986, Nov 24, 2011
Filed:

Dec 14, 2010
Appl. No.:

12/967976
Inventors:

Seung Bum Rim - Palo Alto CA, US
Taeseok Kim - San Jose CA, US
David D. Smith - Campbell CA, US
Peter J. Cousins - Menlo Park CA, US
International Classification:

H01L 29/861
H01L 21/329
US Classification:

257510, 438424, 257E29327, 257E21352
Abstract:

Bypass diodes for solar cells are described. In one embodiment, a bypass diode for a solar cell includes a substrate of the solar cell. A first conductive region is disposed above the substrate, the first conductive region of a first conductivity type. A second conductive region is disposed on the first conductive region, the second conductive region of a second conductivity type opposite the first conductivity type.

Hybrid Polysilicon Heterojunction Back Contact Cell
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US Patent:

20130164879, Jun 27, 2013
Filed:

Dec 21, 2011
Appl. No.:

13/333908
Inventors:

Peter J. Cousins - Menlo Park CA, US
David D. Smith - Campbell CA, US
Seung B. Rim - Palo Alto CA, US
International Classification:

H01L 31/18
H01L 31/0236
US Classification:

438 71, 438 72, 257E31119, 257E3113
Abstract:

A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.

Hybrid Polysilicon Heterojunction Back Contact Cell
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US Patent:

20140080251, Mar 20, 2014
Filed:

Nov 18, 2013
Appl. No.:

14/083141
Inventors:

Peter J. Cousins - Los Altos CA, US
David D. Smith - Campbell CA, US
Seung Bum Rim - Palo Alto CA, US
International Classification:

H01L 31/0236
H01L 31/0368
US Classification:

438 97
Abstract:

A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.

Systems And Methods For Tile Boundary Compensation
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US Patent:

20220375427, Nov 24, 2022
Filed:

Apr 6, 2022
Appl. No.:

17/714805
Inventors:

- Cupertino CA, US
Chaohao Wang - Sunnyvale CA, US
Hopil Bae - Palo Alto CA, US
Mahdi Farrokh Baroughi - Santa Clara CA, US
Wei Chen - Palo Alto CA, US
Wei H Yao - Palo Alto CA, US
Seung B Rim - Pleasanton CA, US
Sunmin Jang - Sunnyvale CA, US
International Classification:

G09G 5/10
Abstract:

An electronic device may display image content via a tile-based display by controlling light emission from display pixels of the tile-based display. Based on image data associated with the image content, a processing circuitry of the tile-based display may receive a potential tile boundary. The processing circuitry may resample the image data based on geometry of the tile boundary and positions of the display pixels on the tile-based panel. After resampling the image data, the processing circuitry may adjust gain of the tile boundary display pixels according to a gain mask to compensate for the tile boundary.

Hybrid Polysilicon Heterojunction Back Contact Cell
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US Patent:

20200365752, Nov 19, 2020
Filed:

Aug 3, 2020
Appl. No.:

16/983770
Inventors:

- San Jose CA, US
David D. Smith - Campbell CA, US
Seung Bum Rim - Palo Alto CA, US
International Classification:

H01L 31/0747
H01L 31/0216
H01L 31/068
H01L 31/18
H01L 31/0236
H01L 31/0368
H01L 31/0224
H01L 31/20
Abstract:

A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.