Shahram Te Mostafazadeh

age ~62

from San Jose, CA

Also known as:
  • Shahram A Mostafazadeh
  • Shahram R Mostafazadeh
  • Shadi A Mostafazadeh
  • Mostafazadeh Shahram
  • Shadi H
Phone and address:
1110 Calcaterra Ct, San Jose, CA 95120
4088937112

Shahram Mostafazadeh Phones & Addresses

  • 1110 Calcaterra Ct, San Jose, CA 95120 • 4088937112
  • 1266 Oakglen Way, San Jose, CA 95120
  • 4238 Monet Cir, San Jose, CA 95136
  • Pebble Beach, CA
  • Carmel, CA
  • Santa Clara, CA
  • 1110 Calcaterra Ct, San Jose, CA 95120
Name / Title
Company / Classification
Phones & Addresses
Shahram Mostafazadeh
Principal
All Electrical and Solar
Electrical Contractor
1110 Calcaterra Ct, San Jose, CA 95120

Us Patents

  • Method For Molding A Bumped Wafer

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  • US Patent:
    6352878, Mar 5, 2002
  • Filed:
    Jun 19, 2000
  • Appl. No.:
    09/596838
  • Inventors:
    Shahram Mostafazadeh - Santa Clara CA
    Joseph O. Smith - Morgan Hill CA
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 2144
  • US Classification:
    438106, 438108, 438127
  • Abstract:
    A method and apparatus for forming a layer of underfill encapsulant on an integrated circuit located on a wafer are described. The integrated circuit has electrically conductive pads, a plurality of which have solder balls attached thereto. To reduce the occurrence of voids during formation of the underfill layer, the wafer is placed in a mold cavity which is evacuated prior to injection of the underfill encapsulant.
  • Method And Apparatus To Enclose Dice

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  • US Patent:
    6420212, Jul 16, 2002
  • Filed:
    Jul 7, 2000
  • Appl. No.:
    09/611245
  • Inventors:
    Shahram Mostafazadeh - San Jose CA
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 2150
  • US Classification:
    438118, 438112, 438124, 438127, 257632, 257783, 257786, 257790, 257797
  • Abstract:
    An improved die cover is provided. The cover is formed from an enclosure with adhesive, which holds a die in the enclosure. The enclosure may be formed as part of a panel of enclosures. The panel of enclosures may be held together by ties. Conventional die attach machinery may be used to place adhesive and dice in the enclosures of the panel of enclosures. The dice may be tested as a panel, and then the enclosures may be singulated.
  • Method To Encapsulate Bumped Integrated Circuit To Create Chip Scale Package

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  • US Patent:
    6468832, Oct 22, 2002
  • Filed:
    Jul 19, 2000
  • Appl. No.:
    09/620206
  • Inventors:
    Shahram Mostafazadeh - San Jose CA
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 2144
  • US Classification:
    438112, 438 26, 438106, 438108, 438127, 257738, 257778
  • Abstract:
    An encapsulated bumped die is provided. Singulated bumped dice are attached to a die attach panel. The die attach panel and dice are placed in a mold, where the bumps are partially flattened. A mold compound is then used to encapsulate the dice and panel. The mold compound is cured. The encapsulated dice are then singulated. The encapsulated dice may then be directly mounted on a substrate such as a PC board. The encapsulation provides added protection to the dice.
  • Lead Frame Chip Scale Package

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  • US Patent:
    6589814, Jul 8, 2003
  • Filed:
    Sep 20, 1999
  • Appl. No.:
    09/399585
  • Inventors:
    Shahram Mostafazadeh - San Jose CA
    Joseph O. Smith - Morgan Hill CA
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 2144
  • US Classification:
    438112, 438111, 438113, 438123, 438124, 257676
  • Abstract:
    A method for producing chip scale IC packages includes the step of mounting a lead frame panel on a temporary support fixture in order to provide support and protection during the manufacturing process. An embodiment of the temporary support fixture includes a sheet of sticky tape secured to a rigid frame. The rigid frame maintains tension in the sheet of sticky tape to provide a stable surface to which the lead frame panel can be affixed. Installation of IC chips and encapsulation in protective casings is performed as in conventional IC package manufacturing. If encapsulant material is to be dispensed over the IC chips, an encapsulant dam can be formed around the lead frame panel to contain the flow of encapsulant material. The temporary support fixture can be used in any IC package manufacturing process in which lead frames require supplemental support.
  • Lead Frame Design For Chip Scale Package

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  • US Patent:
    6683368, Jan 27, 2004
  • Filed:
    Jun 9, 2000
  • Appl. No.:
    09/590551
  • Inventors:
    Shahram Mostafazadeh - San Jose CA
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 23495
  • US Classification:
    257676, 257666
  • Abstract:
    A universal lead frame for mounting dice to form integrated circuit packages is provided. The lead frame may be made from a metal sheet, which may be stamped or etched. The lead frame provides a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are adhesively mounted on to a first set of the plurality of posts. The dice are then electrically connected to a second set of the plurality of posts using wire bonding. An encapsulating material is placed over the dice and lead frame, with the connecting sheet keeping the encapsulating material on one side of the lead frame. The connecting sheet is then removed, leaving the posts as separate leads. The integrated circuits formed by the encapsulated dice and leads may be tested as a panel, before the integrated circuits are singulated.
  • Chip Scale Pin Array

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  • US Patent:
    6689640, Feb 10, 2004
  • Filed:
    Oct 26, 2000
  • Appl. No.:
    09/698736
  • Inventors:
    Shahram Mostafazadeh - San Jose CA
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 2144
  • US Classification:
    438121, 438123, 438124, 257666, 257676
  • Abstract:
    An integrated circuit package with lead fingers with a footprint on the order of the integrated circuit footprint is provided. A lead frame may be made from a metal sheet, which may be stamped or etched. The lead frame provides a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are adhesively mounted to the plurality of posts. The dice have a conductive side with a plurality of conducting pads where each conducting pad is electrically and mechanically connected to a post. An encapsulating material is placed over the dice and lead frame, with the connecting sheet keeping the encapsulating material on one side of the lead frame. Parts of the connecting sheet are then removed, electrically isolating the posts. The integrated circuit packages formed by the encapsulated dice and leads may be tested as a panel, before the integrated circuit packages are singulated.
  • Apparatus And Method Of Manufacturing A Stackable Package For A Semiconductor Device

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  • US Patent:
    6710246, Mar 23, 2004
  • Filed:
    Aug 2, 2002
  • Appl. No.:
    10/211450
  • Inventors:
    Shahram Mostafazadeh - San Jose CA
    Joseph O. Smith - Morgan Hill CA
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 2302
  • US Classification:
    174 523, 361735, 257686
  • Abstract:
    A package, a method of making and a method of assembly of packages for semiconductor chips are disclosed. The package includes a die attach pad on which a semiconductor die is mounted. A lead is electrically connected to the semiconductor die which is encapsulated in packaging material. The lead is exposed at opposed sides of the package. Exposing the lead on both sides of the package allows the package to be stacked or assembled so that the leads of adjacent pairs of packages are in electrical contact. Making the semiconductor packages includes forming a piece of electrically conductive material into a die attach pad and at least one lead associated with the die attach pad. A semiconductor die is mounted on the die attach pad and an electrical connection is made between the semiconductor die and the lead. The package is formed by encapsulation with the lead exposed on opposite sides of the package.
  • Lead Frame Design For Chip Scale Package

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  • US Patent:
    6740961, May 25, 2004
  • Filed:
    Jul 31, 2002
  • Appl. No.:
    10/211130
  • Inventors:
    Shahram Mostafazadeh - San Jose CA
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 23495
  • US Classification:
    257676, 257666, 257777, 257786
  • Abstract:
    A universal lead frame for mounting dice to form integrated circuit packages is provided. The lead frame may be made from a metal sheet, which may be stamped or etched. The lead frame provides a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are adhesively mounted on to a first set of the plurality of posts. The dice are then electrically connected to a second set of the plurality of posts using wire bonding. An encapsulating material is placed over the dice and lead frame, with the connecting sheet keeping the encapsulating material on one side of the lead frame. The connecting sheet is then removed, leaving the posts as separate leads. The integrated circuits formed by the encapsulated dice and leads may be tested as a panel, before the integrated circuits are singulated.

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