Shailendra X Jha from San Jose, CA, age 48

Isbn (Books And Publications)

Agricultural Labour: Present Position and Problems, Legislations, and Governmental Steps, Measures for Upliftment

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Author
Shailendra Jha

ISBN #
8171002153

Resumes

Engineering

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Location:

867 Nichols Cir, Folsom, CA 95630

Industry:

Computer Hardware

Work:

Vexata Jul 2014 - Dec 2017
Senior Technical Director
Apple Jul 2014 - Dec 2017
Engineering
Appliedmicro Sep 2012 - Jul 2014
Senior Manager, Asic Engineering
Brocade Sep 2010 - Aug 2012
Manager, Asic Engineering
Qlogic Jun 2005 - Jan 2010
Principal Asic Design Engineer

Education:

Purdue University 1999 - 2000
Master of Science, Masters, Computer Engineering Indian Institute of Technology, Kharagpur 1994 - 1998

Skills:

Asic
Verilog
Systemverilog
Rtl Design
Soc
Debugging
Vlsi
Tcl
Functional Verification
Timing Closure
Integrated Circuit Design
Static Timing Analysis
Pcie
Formal Verification
Logic Synthesis
Hardware Architecture
Processors
Eda
Computer Architecture
Fpga
Ethernet
Rtl Coding
Ic
Application Specific Integrated Circuits
System on A Chip

Languages:

English

Shailendra Jha

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Shailendra Jha

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Shailendra Kumar Jha

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Us Patents

Multi-Function Pci Device
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US Patent:

20070073955, Mar 29, 2007
Filed:

Sep 29, 2005
Appl. No.:

11/239741
Inventors:

Joseph Murray - Scottsdale AZ, US
Sailesh Bissessur - Phoenix AZ, US
Shailendra Jha - Folsom CA, US
Victor Lau - Marlboro MA, US
Bruno DiPlacido - Westborough MA, US
Suresh Chemudupati - Marlboro MA, US
International Classification:

G06F 13/36
US Classification:

710309000
Abstract:

A multi-function peripheral component interconnect (PCI) device is disclosed. The device includes a first configuration data structure associated with a first PCI function, a second configuration data structure associated with a second PCI function and a PCI bridge, coupled the first and second configuration data structures. The PCI bridge processes transactions on behalf of the first and second functions.

Secure Watchdog Timer
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US Patent:

20040250178, Dec 9, 2004
Filed:

May 23, 2003
Appl. No.:

10/444562
Inventors:

Peter Munguia - Chandler AZ, US
Kyle Gilsdorf - Phoenix AZ, US
Shailendra Jha - Chandler AZ, US
International Classification:

H02H003/05
US Classification:

714/055000
Abstract:

A watchdog timer including a counter, a watchdog enable mechanism, and a timeout control. The watchdog enable mechanism is set to an enabled state by receiving an enabling input and set to a disabled state only by a power cycle or a hardware reset. The timeout control is coupled to the counter and to the watchdog enable mechanism. The timeout control enables a error signal if the watchdog enable mechanism is enabled and the counter is not updated before completing a count.