Shailesh M Kadakia

US Patent:

48230316, Apr 18, 1989

Filed:

Feb 1, 1988

Appl. No.:

7/150954

Inventors:

Shailesh R. Kadakia - Stafford TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 706
G11C 900
G11C 1704
G11C 1140

US Classification:

307530

Abstract:

A single-ended sense amplifier for use in integrated-circuit logic arrays. The sense amplifier circuit uses five field-effect transistors in a unique configuration that uses positive feedback to increase the output speed of response while at the same time allowing layout in the narrow pitch of one bitline of an integrated-circuit logic array.

US Patent:

49637657, Oct 16, 1990

Filed:

Jul 3, 1989

Appl. No.:

7/376920

Inventors:

Shailesh R. Kadakia - Stafford TX
David D. Wilmoth - Sugar Land TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19094
H03K 512

US Classification:

307443

Abstract:

A high speed circuit for detecting input or address transitions at a terminal of an integrated circuit logic array. The circuit utilizes N-channel leaker transistors to control the widths of and P-channel transistors to control the risetimes of output pulses and utilizes inverters and OR circuits to sense input or address transitions of both polarities.

US Patent:

48884987, Dec 19, 1989

Filed:

Mar 24, 1988

Appl. No.:

7/172532

Inventors:

Shailesh R. Kadakia - Stafford TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1100
H03K 301

US Classification:

3072964

Abstract:

A circuit for providing a "power-up" signal pulse in response to energization of an integrated circuit logic array by a power supply. The circuit is comprised of a pulse-generating circuit and of an optional pulse-delay means. The pulse-generating circuit means detects the presence or absence of change in energization voltage potential and, in response to energization, develops an output pulse using ratioed complementary-metal-oxide-semiconductor (CMOS) logic to detect energization status during the ramp increase of the supply voltage. A feedback circuit is used to detect completion of the ramp increase and to deactivate the circuit to minimize power required for steady-state operation. The optional pulse-delay means is illustrated as narrow-width, long-channel CMOS inverters with optional capacitor loading.

US Patent:

51329336, Jul 21, 1992

Filed:

Dec 21, 1990

Appl. No.:

7/631606

Inventors:

John F. Schreck - Houston TX
Shailesh R. Kadakia - Sugar Land TX
Phat C. Truong - Houston TX

International Classification:

G11C 514

US Classification:

365226

Abstract:

A biasing circuit for reading a selected cell of an array of semiconductor memory cells in which each cell is coupled to a drain-column line, a source-column line and a wordline, with the selected cell coupled to a selected drain-column line, a selected source-column line, and a selected wordline. The circuit includes a common node; a resistor means coupled between the common node and each of the source- and drain-column lines; a drain-select means coupled to each drain-column line for transmitting, during a read cycle, a first preselected bias voltage lower than a supply voltage to the selected drain-column line; a source-select means coupled to each source-column line for transmitting, during the read cycle, a second preselected bias voltage to the one non-selected source-column line, the one non-selected source-column line coupled to a cell sharing the selected drain-column line and the selected wordline; and reference-select means for connecting, during the read cycle, the source-column lines, except the one non-selected source-column line, to reference potential. The sense amplifier and the driver circuit each include at least three transistors and have outputs coupled to drain-column lines and source-column lines, respectively, of the memory array.