Shalini A Gupta

US Patent:

20200373384, Nov 26, 2020

Filed:

Aug 13, 2020

Appl. No.:

16/992244

Inventors:

JOSEPHINE BEA CHANG - ELLICOTT CITY MD, US
ERIC J. STEWART - SILVER SPRING MD, US
KEN ALFRED NAGAMATSU - ELLICOTT CITY MD, US
ROBERT S. HOWELL - SILVER SPRING MD, US
SHALINI GUPTA - BALTIMORE MD, US

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION - FALLS CHURCH VA

International Classification:

H01L 29/06
H01L 29/08
H01L 23/29
H01L 23/31
H01L 29/15
H01L 29/423
H01L 21/02
H01L 21/306
H01L 29/778
H01L 29/66

Abstract:

A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.

US Patent:

20200235202, Jul 23, 2020

Filed:

Jan 21, 2019

Appl. No.:

16/252952

Inventors:

JOSEPHINE BEA CHANG - ELLICOTT CITY MD, US
ERIC J. STEWART - SILVER SPRING MD, US
KEN ALFRED NAGAMATSU - ELLICOTT CITY MD, US
ROBERT S. HOWELL - SILVER SPRING MD, US
SHALINI GUPTA - BALTIMORE MD, US

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION - FALLS CHURCH VA

International Classification:

H01L 29/06
H01L 29/08
H01L 23/29
H01L 23/31
H01L 29/15
H01L 29/423
H01L 21/02
H01L 21/306
H01L 29/778
H01L 29/66

Abstract:

A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.

US Patent:

20200013775, Jan 9, 2020

Filed:

Sep 20, 2019

Appl. No.:

16/577629

Inventors:

JUSTIN ANDREW PARKE - ELLICOTT CITY MD, US
ERIC J. STEWART - SILVER SPRING MD, US
ROBERT S. HOWELL - SILVER SPRING MD, US
HOWELL GEORGE HENRY - ELLICOTT CITY MD, US
BETTINA NECHAY - LAUREL MD, US
HARLAN CARL CRAMER - COLUMBIA MD, US
MATTHEW RUSSELL KING - LINTHICUM MD, US
SHALINI GUPTA - Baltimore MD, US
RONALD G. FREITAG - Catonsville MD, US
KAREN MARIE RENALDO - Pasadena CA, US

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION - FALLS CHURCH VA

International Classification:

H01L 27/088
H01L 21/8252
H01L 21/308

Abstract:

A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.

US Patent:

20160104703, Apr 14, 2016

Filed:

Oct 8, 2014

Appl. No.:

14/509750

Inventors:

JUSTIN ANDREW PARKE - ELLICOTT CITY MD, US
ERIC J. STEWART - SILVER SPRING MD, US
ROBERT S. HOWELL - SILVER SPRING MD, US
HOWELL GEORGE HENRY - ELLICOTT CITY MD, US
BETTINA NECHAY - LAUREL MD, US
HARLAN CARL CRAMER - COLUMBIA MD, US
MATTHEW RUSSELL KING - LINTHICUM MD, US
SHALINI GUPTA - FALLS CHURCH VA, US
RONALD G. FREITAG - CATONSVILLE MD, US
KAREN MARIE RENALDO - PASADENA MD, US

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION - FALLS CHURCH VA

International Classification:

H01L 27/088
H01L 29/201
H01L 29/205
H01L 29/06
H01L 21/02
H01L 21/8236
H01L 21/306
H01L 21/8234
H01L 21/308
H01L 29/20
H01L 21/8252

Abstract:

A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.