Sharon Martinez Lin

age ~52

from Redondo Beach, CA

Also known as:
  • Sharon M Lin
  • Sharon M Martinez
  • Sharon Lin Martinez
  • Lin Sharon Martinez
  • Lin S Martinez
Phone and address:
2107 Dufour Ave APT B, Redondo Beach, CA 90278
3109021357

Sharon Lin Phones & Addresses

  • 2107 Dufour Ave APT B, Redondo Beach, CA 90278 • 3109021357
  • Hayward, CA
  • 2107 Dufour Ave APT B, Redondo Beach, CA 90278

Work

  • Position:
    Medical Professional

Education

  • Degree:
    Graduate or professional degree

Lawyers & Attorneys

Sharon Lin Photo 1

Sharon W Lin, Torrance CA - Lawyer

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Address:
1010 Crenshaw Blvd Ste 100, Torrance, CA 90501
3102185500 (Office)
Licenses:
California - Active 2008
Education:
Ucla Sol
Amherst Coll
Specialties:
Litigation - 100%
Sharon Lin Photo 2

Sharon Lin - Lawyer

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Office:
Winston & Strawn LLP
ISLN:
1000781156
Admitted:
2017

Us Patents

  • Converification System And Method

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  • US Patent:
    6389379, May 14, 2002
  • Filed:
    Jun 12, 1998
  • Appl. No.:
    09/096865
  • Inventors:
    Sharon Sheau-Pyng Lin - Cupertino CA
  • Assignee:
    Axis Systems, Inc. - Sunnyvale CA
  • International Classification:
    G06F 9455
  • US Classification:
    703 14, 703 23, 716 5
  • Abstract:
    The coverification system includes a reconfigurable computing system (hereinafter âRCC computing systemâ) and a reconfigurable computing hardware array (hereinafter âRCC hardware arrayâ). In some embodiments, the target system and the external I/O devices are not necessary since they can be modeled in software. In other embodiments, the target system and the external I/O devices are actually coupled to the coverification system to obtain speed and use actual data, rather than simulated test bench data. The RCC computing system contains a CPU and memory for processing data for modeling the entire user design in software. The RCC computing system also contains clock logic (for clock edge detection and software clock generation), test bench processes for testing the user design, and device models for any I/O device that the user decides to model in software instead of using an actual physical I/O device. The user may decide to use actual I/O devices as well as modeled I/O devices in one debug session. The software clock is used as the external clock source for the target system and the external I/O devices to synchronize all data that is delivered between the coverification system and the external interface.
  • Array Board Interconnect System And Method

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  • US Patent:
    6421251, Jul 16, 2002
  • Filed:
    Feb 5, 1998
  • Appl. No.:
    09/019383
  • Inventors:
    Sharon Sheau-Pyng Lin - Cupertino CA 95014
  • International Classification:
    H05K 710
  • US Classification:
    361788, 361803
  • Abstract:
    The FPGA array in the Simulation system is provided on the motherboard through a particular board interconnect structure to provide easy expandability and maximize packaging density with a single PCB design. Each chip may have up to eight sets of interconnections, where the interconnections are arranged according to adjacent direct-neighbor interconnects (i. e. , N[73:0], S[73:0], W[73:0], E[73:0]), and one-hope neighbor interconnects (i. e. , NH[27:0], SH[27:0], XH[36:0], XH[72:37]), excluding the local bus connections, within a single board and across different boards. Each chip is capable of being interconnected directly to adjacent neighbor chips, or in one hop to a non-adjacent chip located above, below, left, and right. In the X direction (east-west), the array is connected in a torus. In the Y direction (north-south), the array is connected in a column.
  • Dynamic Evaluation Logic System And Method

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  • US Patent:
    6651225, Nov 18, 2003
  • Filed:
    Apr 10, 2000
  • Appl. No.:
    09/546554
  • Inventors:
    Sharon Sheau-Pyng Lin - Cupertino CA
    Su-Jen Hwang - Los Altos CA
  • Assignee:
    Axis Systems, Inc. - Sunnyvale CA
  • International Classification:
    G06F 1750
  • US Classification:
    716 4, 716 1
  • Abstract:
    In a verification system, a dynamic logic evaluation system and method dynamically calculates the minimum evaluation time for each input. Thus, this system and method will remove the performance burden that a fixed and statically calculated evaluation time would introduce. By dynamically calculating different evaluation times based on the input, 99% of the inputs will not be delayed for the sake of 1% of the inputs that actually need the worst possible evaluation time. The dynamic logic evaluation system and method comprises a global control unit coupled to a propagation detector, where the propagation detector is placed in each FPGA chip. The propagation detector in the FPGA chip alerts the global control unit of any input data that is currently propagating within the FPGA chips. A master clock controls the operation of this dynamic evaluation system and method. As long as any input data is propagating, the global control unit will prevent the next input from being provided to the FPGA chips for evaluation.
  • Multi-Board Connection System For Use In Electronic Design Automation

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  • US Patent:
    6754763, Jun 22, 2004
  • Filed:
    Mar 6, 2002
  • Appl. No.:
    10/092839
  • Inventors:
    Sharon Sheau-Pyng Lin - Cupertino CA
  • Assignee:
    Axis Systems, Inc. - Sunnyvale CA
  • International Classification:
    G06F 1340
  • US Classification:
    710317, 710305, 361748, 712 33, 370257
  • Abstract:
    A high fan-out hub array system and method is provided. The system includes at least one hub that contains user logic that receive signals from various chips and boards, and which quickly turnarounds another signal (based on the logic) out to the desired chips and boards. In a CLKGEN implementation, a global clock is generated in the hub and distributed in a high fan-out manner to all the FPGA logic chips in the system. For a bus resolution application, a hub contains bus resolution logic to resolve bus access requests. It resolves the various requests and delivers the result to all the relevant chips and boards. In a STOPWHEN application, when a STOPWHEN condition has been met, the system delivers a pause signal to all the chips and boards via the high fan-out hubs.
  • Memory Mapping System And Method

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  • US Patent:
    6810442, Oct 26, 2004
  • Filed:
    Sep 12, 2001
  • Appl. No.:
    09/954275
  • Inventors:
    Sharon Sheau-Pyng Lin - Cupertino CA
  • Assignee:
    Axis Systems, Inc. - Sunnyvale CA
  • International Classification:
    G06F 1328
  • US Classification:
    710 22, 710 52, 703 27
  • Abstract:
    A debug system generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device for used in electronic design automation (EDA). The FPGA device (Behavior Processor) operates to execute in hardware code constructs previously executed in software. When some condition is satisfied (e. g. If. . . then. . . else loop) requiring intervention, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response. A memory block from a logic device is mapped to a memory device in a re-configurable hardware unit using a memory mapping system including a conductive connector driver, a memory block interface, and evaluation logic in each logic device, the connector driver, the interface, and the connector controller, the evaluation logic providing control signals used to evaluate data in the hardware model and to control write/read memory access between the logic device and the memory device via the driver and interface.
  • Multi-User Server System And Method

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  • US Patent:
    7505891, Mar 17, 2009
  • Filed:
    May 20, 2003
  • Appl. No.:
    10/442850
  • Inventors:
    Sharon Sheau-Pyng Lin - Cupertino CA, US
  • Assignee:
    Verisity Design, Inc. - Mountain View CA
  • International Classification:
    G06F 9/455
  • US Classification:
    703 27
  • Abstract:
    The multi-user server technology allows multiple host stations to configure, load, and execute multiple jobs in a reconfigurable hardware unit for emulation purposes, simulation acceleration purposes, and a combination of emulation and simulation in a concurrent manner. The reconfigurable hardware unit includes a plurality of hardware resources (e. g. , FPGA chips on slot module boards) for modeling at least a portion of one or more user design. The server includes a bus arbiter for deciding which one of the host stations will be coupled to the hardware resources via the bus multiplexer. The plurality of hardware resources includes slot modules, which includes one or more boards of FPGA chips. An arbitration decision is made to assign a particular slot(s) to a particular host. A host and its respective assigned slot(s) can communicate with each other while other hosts and their respective assigned slot(s) communicate with each other.
  • Method And Apparatus For Simulating A Circuit Using Timing Insensitive Glitch-Free (Tigf) Logic

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  • US Patent:
    8244512, Aug 14, 2012
  • Filed:
    Sep 12, 2001
  • Appl. No.:
    09/954989
  • Inventors:
    Sharon Sheau-Pyng Lin - Cupertino CA, US
    Quincy Kun-Hsu Shen - Saratoga CA, US
    Mike Mon Yen Tsai - Los Altos Hills CA, US
    Steven Wang - Cupertino CA, US
  • Assignee:
    Cadence Design Systems, Inc. - San Jose CA
  • International Classification:
    G06F 17/50
  • US Classification:
    703 14, 703 13
  • Abstract:
    The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e. g. , If. . . then. . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.
  • Common Shared Memory In A Verification System

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  • US Patent:
    20110307233, Dec 15, 2011
  • Filed:
    Apr 1, 2011
  • Appl. No.:
    13/078786
  • Inventors:
    Sharon Sheau-Pyng Lin - Cupertino CA, US
    Quincy Kun-Hsu Shen - Saratoga CA, US
    Mike Mon Yen Tsai - Los Altos Hills CA, US
    Steven Wang - Cupertino CA, US
  • International Classification:
    G06F 17/50
  • US Classification:
    703 14, 703 13, 703 21
  • Abstract:
    The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.
Name / Title
Company / Classification
Phones & Addresses
Sharon Lin
Maxreal
Real Estate Agents and Managers
1288 Kifer Rd Ste 208, Sunnyvale, CA 94086
Sharon Lin
Marketing Manager
Intuit Inc
Accounting/Auditing/Bookkeeping
21215 Burbank Blvd, Woodland Hills, CA 91367
8187165052
Sharon Liu Lin
Sharon Lin MD
Anesthesiology
PO Box 951778, Los Angeles, CA 90095
3102066766
Sharon Lin
Maxreal
Loan Broker
1288 Kifer Rd, Sunnyvale, CA 94086
4082128800, 4082128788, 4086664521
Sharon Lin
President
MCFERRAN HOME FURNISHINGS INC
Ret Furniture
4850 Eucalyptus Ave, Chino, CA 91710
14237 Don Julian Rd, Whittier, CA 91746
9095978886, 6269619388
Sharon Chan Lin
President
Rosa Express (Lax) Inc
5520 Maricopa St, Torrance, CA 90503
Sharon Lin
President
ADVANCED SOFTWARE CONSULTANTS, INC
29001 Catherwod Ct, Agoura Hills, CA 91301
29001 Catherwood Ct, Calabasas, CA 91301
Sharon Lin
President
SHARON LIN, A PROFESSIONAL CORPORATION
21009 New Hampshire Ave, Torrance, CA 90502

Resumes

Sharon Lin Photo 3

Sharon Lin Yorba Linda, CA

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Work:
Self

Mar 2013 to 2000
Private Tutor
Steps Academy

Oct 2009 to 2000
Supervisor
Tutti Frutti

Oct 2008 to Dec 2009
Food Service Representative
Life Plaza

Oct 2007 to Dec 2009
Sales Representative
Education:
California State University Los Angeles
Los Angeles, CA
2006 to 2014
BS in Mechanical Engineering
California State University Los Angeles
Los Angeles, CA
2006 to 2014
BS in Engineering with emphasis in Manufacturing
Skills:
Computer - SolidWorks, MATLAB, AutoCAD, Fortran, Microsoft Office, Word, and Excel<br/>Fabrication - Wood shop and machining<br/>Languages - English and Mandarin Chinese

Medicine Doctors

Sharon Lin Photo 4

Dr. Sharon Lin, San Rafael CA - DO (Doctor of Osteopathic Medicine)

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Specialties:
Family Medicine
Address:
3110 Kerner Blvd, San Rafael, CA 94901
4154481500 (Phone), 4155268553 (Fax)

3569 Round Barn Cir Suite 200, Santa Rosa, CA 95403
7073033600 (Phone), 7073033611 (Fax)
Certifications:
Family Practice, 2011
Awards:
Healthgrades Honor Roll
Languages:
English
Education:
Medical School
Touro University College Of Osteopathic Medicine
Graduated: 2008

Isbn (Books And Publications)

Libraries and Librarianship in China

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Author
Sharon Chien Lin

ISBN #
0313289379

Real Estate Brokers

Sharon Lin Photo 5

Sharon Lin, Alhambra CA Agent

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Work:
Century 21
Alhambra, CA
6262893505 (Phone)

Googleplus

Sharon Lin Photo 6

Sharon Lin

Lived:
Berkeley, CA
Pleasanton, CA
Work:
Cal Athletics
DeWeese Lab (2013)
Education:
University of California, Berkeley - Nutritional Science
Sharon Lin Photo 7

Sharon Lin

Education:
Croydon Secondary College - VCE, Norwood Secondary College - Mainstream schooling, Hawthorn Secondary College - Mainstream schooling, Croydon Secondary College - Mainstream schooling, Mordialloc College - Mainstream schooling
Bragging Rights:
Dylan miller's missus. 13.11.2010 ♥
Sharon Lin Photo 8

Sharon Lin

Work:
Amigurumi Frenzy
About:
Here's some stuff to get to know me :) Blammo Goddess CTY.LAN.14.2 Obssessed with bakingKawaii!I <3 infinity scarvesFav Color: PurpleTortoises! Rawr
Tagline:
I write stuff.
Bragging Rights:
Author of Hidden
Sharon Lin Photo 9

Sharon Lin

Education:
Turtle rock elementary, Rancho san joaquin intermediate school
About:
Hewo my name is sharon~ ahahahahaha <3 u all!!!!!!
Sharon Lin Photo 10

Sharon Lin

Lived:
Cupertino, CA
Education:
University of California, Berkeley - Economics & Statistics
Sharon Lin Photo 11

Sharon Lin

Work:
ClickSoftware Technologies Ltd. - Software Engineer (2009)
Tagline:
Everything under the sun is in tune but the sun is eclipsed by the moon
Sharon Lin Photo 12

Sharon Lin

Work:
Century 21 Real Estate - Real Estate Agent
C21 Earnest Realty
Sharon Lin Photo 13

Sharon Lin

Education:
University of California, Davis
Tagline:
Holla holla fo' a dolla
Bragging Rights:
I can do nothing for a very long time

Youtube

How to Write a Poem: Lessons in Perception an...

Poetry, Empathy, Problem Solving, Perception, Education, Youth This ta...

  • Duration:
    8m 8s

Sharon Lin & Bhikkhu Bodhi

The Venerable Bhikkhu Bodhi speaks with Sharon Lin, Buddhist Global Re...

  • Duration:
    2m 56s

Graduation 2015 MIDS Student Speaker: Sharon ...

UC Berkeley School of Information Commencement May 16, 2015 Student sp...

  • Duration:
    5m 40s

Youth Poet Laureate winner Sharon Lin (1st po...

Recorded Dec 17, 2016 at the New York Public Library The views and opi...

  • Duration:
    1m 25s

Sharon Lin Callahan 2015

  • Duration:
    3m 25s

2022 641

  • Duration:
    5m 40s

Myspace

Sharon Lin Photo 14

Sharon Lin

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Locality:
Jakarta, Indonesia
Gender:
Female
Birthday:
1947
Sharon Lin Photo 15

sharon lin

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Locality:
shanghai, Taiwan
Gender:
Female
Birthday:
1945
Sharon Lin Photo 16

Sharon Lin

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Locality:
scarborough, Canada
Gender:
Female
Birthday:
1950
Sharon Lin Photo 17

Sharon Lin

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Locality:
Taiwan
Gender:
Female
Birthday:
1949

Plaxo

Sharon Lin Photo 18

Lian May Lin, Sharon

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Education Environment & Customer Care Manager at E...

Flickr

Classmates

Sharon Lin Photo 27

Sharon Lin

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Schools:
Illinois Mathematics & Science Academy Aurora IL 1992-1995, Winsor School Boston MA 1993-1995
Community:
Marlon Hall, Kerri Lockhart, Jenny Gable, Marina Sivilay
Sharon Lin Photo 28

Sharon Lin

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Schools:
Fisherville Junior High School North York Morocco 1993-1995
Community:
Cindi Mcgonigle, Marlene Zeidenberg, Penny Rush
Sharon Lin Photo 29

Cary Academy, Cary, North...

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Graduates:
Sharon Lin (1998-2002),
William Hussey (2002-2006),
Kayle Salter (2003-2007),
Zak Davis (1993-1997),
Robert Smith (1999-2003)
Sharon Lin Photo 30

Queen's University - Arts...

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Graduates:
Sharon Lin (1999-2003),
Sandra McCrudden (1954-1957),
Dean Nicholson (1981-1985),
Rhea Brandenburg (2001-2004),
David Rogers (1987-1991)
Sharon Lin Photo 31

Fisherville Junior High S...

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Graduates:
Ruben Abecassis (1982-1986),
Josie Schreiber (1969-1973),
Sharon Lin (1993-1995),
Annette Rubinov (2002-2003),
Chessa Rosenberg (1969-1972)
Sharon Lin Photo 32

Illinois Mathematics &amp...

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Graduates:
Sharon Lin (1992-1995),
Richard Park (1991-1994),
Jeff Dodge (1986-1989),
Tiffany Gholar (1993-1997),
Dave Lin (1989-1993),
Jennifer Urbauer (1995-1998)
Sharon Lin Photo 33

Winsor School, Boston, Ma...

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Graduates:
Genevieve Laforet (1968-1976),
Elizabeth Bornheimer (1989-1992),
Claire Brassert (1979-1985),
Sharon Lin (1993-1995)
Sharon Lin Photo 34

University of California ...

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Graduates:
Sharon Lin (1989-1993),
Patrick Nguyen (2002-2004),
Taryn Townsend (1999-2002),
Steven Jacobsohn (1975-1979),
Oliver Rheinfurth (1978-1983)

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