Shaw C Lee

US Patent:

6362530, Mar 26, 2002

Filed:

Apr 6, 1998

Appl. No.:

09/056074

Inventors:

Shaw Wei Lee - Cupertino CA
Hem P. Takiar - Fremont CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 2348

US Classification:

257778, 257704

Abstract:

A method of forming an integrated circuit package includes providing a flip chip integrating circuit die having a first plurality of contacts for electrically connecting the die to other elements. A second plurality of contacts for electrically connecting the integrated circuit package to external elements is also provided. A substrate for supporting the flip chip die and the second plurality of contacts is initially prepared. The substrate includes a connecting arrangement for electrically connecting the first plurality of contacts on the die to the second plurality of contacts. The method includes the step positioning the flip chip integrated circuit die and the second plurality of contacts on the substrate. With the flip chip die and the second plurality of contacts in position, both the first plurality of contacts on the flip chip die and the second plurality of contacts are simultaneously attached to the substrate thereby electrically connecting the die and the second plurality of contacts to the substrate. In one embodiment, a metal cap is attached to the integrated circuit package to cover and protect the die.

US Patent:

6396135, May 28, 2002

Filed:

Dec 21, 2000

Appl. No.:

09/748309

Inventors:

Glenn C. Narvaez - Redwood City CA
Shaw Wei Lee - Cupertino CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 2302

US Classification:

257678, 257783, 438106

Abstract:

A number of techniques and substrate arrangements are described that working individually and in common have been found to significantly improve the environmental resistance of the resulting package. In one aspect, conductive pads (referred to herein as landing pads) on the top surface of a substrate are slightly undercut. This permits molding material applied during later packaging to flow into the undercut regions to help improve adhesion between the substrate and the molding material. In another aspect, metallic die attach pads formed on the substrate are patterned to provide better adhesion between the substrate and a solder mask that covers the die attach pads. More specifically, the metallic die attach pads are patterned to have a number of opening defined therein that leave corresponding portions of the substrate exposed. In substrates where a solder mask is applied over the die attach pad, the openings permit the solder mask to adhere directly to the substrate panel in the openings thereby strengthening the attachment of the solder mask to the substrate. In still another aspect, elongated slots are provided in the solder mask such that the slots expose one or more rows of adjacent landing pads instead of simply the landing pads themselves.

US Patent:

6723585, Apr 20, 2004

Filed:

Oct 31, 2002

Appl. No.:

10/286320

Inventors:

Nghia Tu - San Jose CA
Shaw Wei Lee - Cupertino CA
Sadanand R. Patil - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 2144

US Classification:

438123, 438106, 438121, 257666, 257687, 257678, 257701, 257121, 174 522, 174 524

Abstract:

A variety of leadless packaging arrangements and methods of packaging integrated circuits in leadless packages are disclosed. The described lead frames are generally arranged such that each device area has a plurality of contacts but no die attach pad. With this arrangement, the back surface of the die is exposed and coplanar with the exposed bottom surface of the contacts. A casing material (typically plastic) holds the contacts and die in place. In one aspect of the invention, the back surface of the die is metallized. The metallization forms a good attachment surface for the package and serves as a good thermal path to transfer heat away from the die. In another aspect, at least some of the contacts have a top surface, a shelf, and a bottom surface. The die is wire bonded (or otherwise electrically connected) to the shelf portions of the contacts. The described package is quite versatile.

US Patent:

6873024, Mar 29, 2005

Filed:

Aug 9, 2002

Appl. No.:

10/217341

Inventors:

Ashok Prabhu - San Jose CA, US
Shaw Wei Lee - Cupertino CA, US

Assignee:

Eastman Kodak Company - Rochester NY

International Classification:

H01L031/0232
H01L023/02
H01L023/24

US Classification:

257434, 257433, 257680, 257687, 257432

Abstract:

An apparatus and method for wafer level packaging of optical imaging die using conventional semiconductor packaging techniques. The method comprises forming spacing structures over imaging circuitry on a plurality of dice on a semiconductor wafer, attaching a transparent template on the spacing structures on the plurality dice on the semiconductor wafer, singulating the plurality of dice on the semiconductor wafer, and packaging the plurality of dice after being singulated from the wafer. The apparatus comprises a semiconductor wafer including a plurality of dice, each of the dice including imaging circuitry and bond pads. A translucent template is positioned over the semiconductor wafer. The translucent plate includes die cover regions configured to cover the imaging circuitry of the dice and recess regions to exposed the bond pads of the dice respectively. The resulting chip, after further packaging steps, includes the substrate, the semiconductor die having imaging circuitry and bond pads, the semiconductor die mounted onto the substrate and the transparent template positioned over the semiconductor die. The transparent template includes the a die cover region configured to be positioned over the imaging circuitry of the semiconductor die and recess regions to expose the bond pads of the semiconductor die.

US Patent:

6933212, Aug 23, 2005

Filed:

Jan 13, 2004

Appl. No.:

10/757303

Inventors:

Shaw Wei Lee - Cupertino CA, US
Nghia T. Tu - San Jose CA, US
Sadanand Patil - San Jose CA, US
Visvamohan Yegnashankaran - Redwood City CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L021/301

US Classification:

438464, 438462, 438460, 438459

Abstract:

A method and apparatus for the dicing of semiconductor wafers using pressure to mechanically separate the individual die from the wafer without the use of a wafer saw. The method includes forming trenches along the scribe lines on a semiconductor wafer and then applying a mechanical pressure to the semiconductor wafer. The mechanical pressure causes a “clean break” of the wafer along the scribe lines, thereby singulating individual die on the wafer. The apparatus comprises a pad for supporting a semiconductor wafer and a positioning member to position the semiconductor wafer on the pad. A pressure mechanism is provided to apply a mechanical pressure to the wafer so as to singulate the individual die on the wafer.

US Patent:

7087986, Aug 8, 2006

Filed:

Jun 18, 2004

Appl. No.:

10/871313

Inventors:

Jaime A. Bayan - Palo Alto CA, US
Ashok S. Prabhu - San Jose CA, US
Shaw Wei Lee - Cupertino CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 23/495
H01L 23/04

US Classification:

257676, 257698, 257E23037

Abstract:

A solder pad configuration for use in an IC package is described. Various embodiments of the invention describe IC packages, lead-frames, or substrate panels configured with generally noncircular solder pads at their bottom surfaces. The noncircular shapes allow for greater surface area than circular solder pads having diameters equal to a major dimension of the noncircular shapes, while maintaining the same metal-to-metal clearance between the pads and adjacent leads. This increased surface area provides for stronger and more reliable solder joints.

US Patent:

7161232, Jan 9, 2007

Filed:

Sep 14, 2004

Appl. No.:

10/942061

Inventors:

Shaw Wei Lee - Cupertino CA, US
Nghia Thuc Tu - San Jose CA, US
Santhiran S/O Nadarajah - Melaka, MY
Lim Peng Soon - Melaka, MY

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 23/495

US Classification:

257676, 257E23039, 257678, 257668, 257684

Abstract:

A method and apparatus for making reliable miniature semiconductor packages having a reduced height and footprint is provided. The package includes a semiconductor chip having an active surface and a non-active surface and one or more contacts positioned adjacent the semiconductor chip. Electrical connections are formed between the contacts and the semiconductor chip. An adhesive tape provided adjacent the non-active surface of the semiconductor chip and the one or more contacts positioned adjacent the semiconductor chip. An adhesive material provided between the non-active surface of the chip and the adhesive tape.

US Patent:

7205095, Apr 17, 2007

Filed:

Sep 17, 2003

Appl. No.:

10/666921

Inventors:

Ashok Prabhu - San Jose CA, US
Shaw Wei Lee - Cupertino CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G03C 5/00
H01L 31/0203

US Classification:

430311, 257434, 257433, 257435, 250239, 2502081

Abstract:

An method and apparatus for fabricating a die having imaging circuitry and fabricating a lid having a transparent region and support regions having a predetermined height. The lid is fabricated by applying a photo-sensitive adhesive layer with a thickness substantially equal to the predetermined height to a transparent plate and patterning the photo-sensitive adhesive layer to form the transparent region and the support regions. Once fabrication of the lid is complete, it is mounted directly onto the die so that the transparent region generally covers the imaging circuitry. The resulting apparatus includes a lid mounted directly onto the die with the transparent region generally positioned above the imaging circuitry. A gap, having a height dimension substantially equal to the predetermined height of the support regions of the lid, is spaced between the transparent region of the lid and the imaging circuitry on the die.