Shawn R Carpenter

US Patent:

58621490, Jan 19, 1999

Filed:

Oct 3, 1996

Appl. No.:

8/726332

Inventors:

Shawn R. Carpenter - Minneapolis MN
Thomas S. Valind - New Brighton MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G01R 3128

US Classification:

371 223

Abstract:

A method used by an electronic design automation system for partitioning the logic design of an integrated circuit and generating test patterns for testing the integrated circuit. The logic design of the integrated circuit includes a gate-level description having components and nets. Nets include base nets input to the integrated circuit and apex nets output from the integrated circuit. The nets are specified by vector net notation. The method includes creating a plurality of cones of logic design from the logic design of the integrated circuit. Each cone is defined by tracing a path from an apex net, defined by a logic designer, output from a logical register of the logic design to a logic designer-defined base net affecting the logical register. A test pattern is then automatically generated for each of the traced cones of logic design. Logic cone tracing and partitioning the logic design of integrated circuits according to logical registers specified by vector net notation decreases automatic test pattern generation time in an electronic design automation system.

US Patent:

58020756, Sep 1, 1998

Filed:

Jan 16, 1997

Appl. No.:

8/783344

Inventors:

Shawn R. Carpenter - Minneapolis MN
Samuel J. Lewis - Andover MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1100

US Classification:

371 271

Abstract:

A method and apparatus for automatically generating test patterns for a circuit design using a number of data processing elements. The present invention reduces the wall time required to generate the test patterns for the overall circuit design by partitioning the design into a number of partitions, distributing the partitions to a number of data processing elements, and generating test patterns for each partition on the corresponding data processing elements. The present invention automatically assembles the resulting local test patterns to reflect the scan structure of the overall circuit design.