Shawn A Hamilton

US Patent:

7960297, Jun 14, 2011

Filed:

Dec 7, 2006

Appl. No.:

11/608185

Inventors:

Michael Rivkin - Sunnyvale CA, US
Ron Powell - Portola Valley CA, US
Shawn Hamilton - Boulder Creek CA, US
Michael Nordin - San Jose CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 21/00
B05B 5/00

US Classification:

438800, 118640

Abstract:

A semiconductor processing tool heats wafers using radiant heat and resistive heat in chamber or in a load lock where pressure changes. The wafers are heated in greater part with a resistive heat source until a transition temperature or pressure is reached, then they are heated in greater part with a radiant heat source. Throughput improves for the tool because of the wafers can reach a high temperature uniformly in seconds.

US Patent:

8033769, Oct 11, 2011

Filed:

Nov 30, 2007

Appl. No.:

11/998528

Inventors:

Chris Gage - Campbell CA, US
Shawn Hamilton - Boulder Creek CA, US
Sheldon Templeton - San Jose CA, US
Keith Wood - Sunnyvale CA, US
Damon Genetti - Livermore CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 21/677

US Classification:

414217, 414805, 414935

Abstract:

Provided are apparatuses and methods disclosed for wafer processing. Specific embodiments include dual wafer handling systems that transfer wafers from storage cassettes to processing modules and back and aspects thereof. Stacked independent loadlocks that allow venting and pumping operations to work in parallel and may be optimized for particle reduction are provided. Also provided are annular designs for radial top down flow during loadlock vent and pumpdown.

US Patent:

8052419, Nov 8, 2011

Filed:

Nov 8, 2007

Appl. No.:

11/937364

Inventors:

Michael Nordin - San Jose CA, US
Chris Gage - Campbell CA, US
Shawn Hamilton - Boulder Creek CA, US
Sheldon Templeton - San Jose CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H05B 3/68

US Classification:

432247, 118729, 2194431

Abstract:

Methods and apparatuses that decouple wafer temperature from pre-heat station residence time, thereby improving wafer-to-wafer temperature uniformity, are provided. The methods involve maintaining a desired temperature by varying the distance between the wafer and a heater. In certain embodiments, the methods involve rapidly approaching a predetermined initial distance and then obtaining and maintaining a desired final temperature using closed loop temperature control. In certain embodiments, a heated pedestal supplies the heat. The wafer-pedestal gap may be modulated may be varied by moving the heated pedestal and/or moving the wafer, e. g. , via a movable wafer support. Also in certain embodiments, the closed loop control system includes a real time wafer temperature sensor and a servo controlled linear motor for moving the pedestal or wafer support.

US Patent:

8273670, Sep 25, 2012

Filed:

May 6, 2011

Appl. No.:

13/102858

Inventors:

Michael Rivkin - Los Altos CA, US
Ron Powell - Portola Valley CA, US
Shawn Hamilton - Boulder Creek CA, US
Michael Nordin - San Jose CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 21/00
B05B 5/00

US Classification:

438800, 118640

Abstract:

A semiconductor processing tool heats wafers using radiant heat and resistive heat in chamber or in a load lock where pressure changes. The wafers are heated in greater part with a resistive heat source until a transition temperature or pressure is reached, then they are heated in greater part with a radiant heat source. Throughput improves for the tool because of the wafers can reach a high temperature uniformly in seconds.

US Patent:

8491248, Jul 23, 2013

Filed:

Sep 9, 2011

Appl. No.:

13/229497

Inventors:

Chris Gage - Campbell CA, US
Shawn Hamilton - Boulder Creek CA, US
Sheldon Templeton - San Jose CA, US
Keith Wood - Sunnyvale CA, US
Damon Genetti - Livermore CA, US

Assignee:

Novellus Systems, Inc. - Fremont CA

International Classification:

H01L 21/677

US Classification:

414217, 414805, 414935

Abstract:

Provided are apparatuses and methods disclosed for wafer processing. Specific embodiments include dual wafer handling systems that transfer wafers from storage cassettes to processing modules and back and aspects thereof. Stacked independent loadlocks that allow venting and pumping operations to work in parallel and may be optimized for particle reduction are provided. Also provided are annular designs for radial top down flow during loadlock vent and pumpdown.

US Patent:

20090142163, Jun 4, 2009

Filed:

Nov 30, 2007

Appl. No.:

11/998857

Inventors:

Damon Genetti - Livermore CA, US
Shawn Hamilton - Boulder Creek CA, US
Rich Blank - San Jose CA, US
Sheldon Templeton - San Jose CA, US

International Classification:

H01L 21/67

US Classification:

414217, 414805, 901 2

Abstract:

Methods and systems for positioning wafers using a dual side-by-side end effector robot are provided. The methods involve performing place moves using dual side-by-side end effector robots with active wafer position correction. According to various embodiments, the methods may be used for placement into a process module, loadlock or other destination by a dual wafer transfer robot. The methods provide nearly double the throughput of a single wafer transfer schemes by transferring two wafers with the same number of moves.

US Patent:

20120161405, Jun 28, 2012

Filed:

Dec 16, 2011

Appl. No.:

13/329078

Inventors:

Jonathan D. Mohn - Saratoga CA, US
Harald te Nijenhuis - San Jose CA, US
Shawn M. Hamilton - Boulder Creek CA, US
Kevin Madrigal - Santa Cruz CA, US
Ramkishan Rao Lingampalli - Fremont CA, US

International Classification:

B23B 31/02

US Classification:

279142

Abstract:

Electronic device fabrication processes, apparatuses and systems for flowable gap fill or flowable deposition techniques are described. In some implementations, a semiconductor fabrication chamber is described which is configured to maintain a semiconductor wafer at a temperature near 0 C. while maintaining most other components within the fabrication chamber at temperatures on the order of 5-10 C. or higher than the wafer temperature.

US Patent:

20140049162, Feb 20, 2014

Filed:

Aug 15, 2012

Appl. No.:

13/586790

Inventors:

George Thomas - Fremont CA, US
Bart van Schravendijk - Sunnyvale CA, US
Harald Te Nijenhuis - San Jose CA, US
Shawn Hamilton - Boulder Creek CA, US
Konstantin Makhratchev - Fremont CA, US

International Classification:

H05H 1/24

US Classification:

31511121

Abstract:

Methods and apparatus to reduce particle-induced defects on a substrate are provided. In certain embodiments, the methods involve decreasing plasma spread prior to extinguishing the plasma. The plasma is maintained at the decreased plasma spread while particles are evacuated from the processing chamber. In certain embodiments, the methods involve decreasing plasma power prior to extinguishing the plasma. The low-power plasma is maintained while particles are evacuated from the processing chamber.