Shawn Robert Thomas

US Patent:

6636857, Oct 21, 2003

Filed:

Dec 17, 2002

Appl. No.:

10/321115

Inventors:

Shawn Thomas - Austin TX
Gregory Gray - Austin TX
Michael Woodfin - Austin TX
Warner Mizell - Austin TX
Brian Thomas - Austin TX

Assignee:

Bluecurrent, Inc. - Austin TX

International Classification:

G06F 1730

US Classification:

707 10, 709209, 711173, 717 11, 717173, 713200, 713182

Abstract:

The method and system of the present invention provides an improved technique for replacing, implementing and managing computer-related assets. A technician accesses the World Wide Web through a users computer. The information resident on the computer, including information regarding the computer and the users preferences, are downloaded to a remote storage medium through the World Wide Web. Once downloaded, all information may be removed from the users computer. Subsequently, the technician accesses another computer such as, for example, a new computer that has been assigned to the same user. The technician accesses the World Wide Web through the new computer and downloads the information previously stored on the remote storage medium. This information can then be used to install the users prior applications, settings and preferences on the new computer.

US Patent:

6831350, Dec 14, 2004

Filed:

Oct 2, 2003

Appl. No.:

10/677844

Inventors:

Chun-Li Liu - Mesa AZ
Alexander L. Barr - Austin TX
John M. Grant - Austin TX
Marius K. Orlowski - Austin TX
Tab A. Stephens - Austin TX
Ted R. White - Austin TX
Shawn G. Thomas - Gilbert AZ

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 2930

US Classification:

257617, 257616, 257241, 257243, 257288, 257368, 438149, 438150, 438151, 438163, 438197, 438430, 438517

Abstract:

A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness. Each adjoining layer of the plurality of layers forms an interface for promoting defects in the transition zone to migrate to and terminate on an edge of the programmed transition zone. A method of making the same is also disclosed.

US Patent:

7029980, Apr 18, 2006

Filed:

Sep 25, 2003

Appl. No.:

10/670928

Inventors:

Chun-Li Liu - Mesa AZ, US
Marius K. Orlowski - Austin TX, US
Matthew W. Stoker - Mesa AZ, US
Philip J. Tobin - Austin TX, US
Mariam G. Sadaka - Austin TX, US
Alexander L. Barr - Austin TX, US
Shawn G. Thomas - Gilbert AZ, US
Ted R. White - Austin TX, US

Assignee:

Freescale Semiconductor Inc. - Austin TX

International Classification:

H01L 21/331

US Classification:

438311, 438479, 438404, 438459

Abstract:

A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.

US Patent:

7056778, Jun 6, 2006

Filed:

Aug 17, 2004

Appl. No.:

10/919784

Inventors:

Chun-Li Liu - Mesa AZ, US
Mariam G. Sadaka - Austin TX, US
Alexander L. Barr - Crolles, FR
Shawn G. Thomas - Gilbert AZ, US
Ted R. White - Austin TX, US
Qianghua Xie - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/338

US Classification:

438184, 438200

Abstract:

A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e. g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e. g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.

US Patent:

7241647, Jul 10, 2007

Filed:

Aug 17, 2004

Appl. No.:

10/919952

Inventors:

Mariam G. Sadaka - Austin TX, US
Shawn G. Thomas - Gilbert AZ, US
Ted R. White - Austin TX, US
Chun-Li Liu - Mesa AZ, US
Alexander L. Barr - Crolles, FR

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00

US Classification:

438149, 438DIG 933, 438DIG 967, 257E21093, 257E21561

Abstract:

A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.

US Patent:

7282402, Oct 16, 2007

Filed:

Mar 30, 2005

Appl. No.:

11/093801

Inventors:

Mariam G. Sadaka - Austin TX, US
Alexander L. Barr - Crolles, FR
Dejan Jovanovic - Austin TX, US
Shawn G. Thomas - Gilbert AZ, US
Ted R. White - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/8238
H01L 21/336

US Classification:

438221, 438197, 438199, 438230, 438202, 438258, 438303, 438207, 438218, 257E2163, 257E21631, 257E21632, 257E21633, 257E21634, 257E21635, 257E21636, 257E21637, 257E21638, 257E21639, 257E2164, 257E21641, 257E21642, 257E21643, 257E21644

Abstract:

According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

US Patent:

7320931, Jan 22, 2008

Filed:

Jul 30, 2004

Appl. No.:

10/903841

Inventors:

Shawn G. Thomas - Gilbert AZ, US
Vida Ilderem - Phoenix AZ, US
Papu D. Maniar - Mesa AZ, US

Assignee:

Freescale Semiconductor Inc. - Austin TX

International Classification:

H01L 29/72

US Classification:

438503, 438471, 438478, 438585, 257310, 257407, 257410, 257532, 257616

Abstract:

Methods and apparatus are provided for depositing a layer of pure germanium can on a silicon substrate. This germanium layer is very thin, on the order of about 14 Å, and is less than the critical thickness for pure germanium on silicon. The germanium layer serves as an intermediate layer between the silicon substrate and the high k gate layer, which is deposited on the germanium layer. The germanium layer helps to avoid the development of an oxide interfacial layer during the application of the high k material. Application of the germanium intermediate layer in a semiconductor structure results in a high k gate functionality without the drawbacks of series capacitance due to oxide impurities. The germanium layer further improves mobility.

US Patent:

7759199, Jul 20, 2010

Filed:

Sep 19, 2007

Appl. No.:

11/858054

Inventors:

Shawn Thomas - Gilbert AZ, US
Pierre Tomasini - Tempe AZ, US

Assignee:

ASM America, Inc. - Phoenix AZ

International Classification:

H01L 21/336

US Classification:

438269, 438300, 438360, 438429, 257E2143, 257E21461, 257E21634

Abstract:

A semiconductor substrate having recesses filled with heteroepitaxial silicon-containing material with different portions having different impurity concentrations. Strained layers can fill recessed source/drain regions in a graded, bottom-up fashion. Layers can also line recess sidewalls with one concentration of strain-inducing impurity and fill the remainder to the recess with a lower concentration of the impurity. In the latter case, the sidewall liner can be tapered.