Shawn Xianggang Yu

US Patent:

7408485, Aug 5, 2008

Filed:

Mar 22, 2007

Appl. No.:

11/726414

Inventors:

Shawn Xianggang Yu - Austin TX, US
Terry L. Sculley - Austin TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 7/00

US Classification:

341 61, 708313, 708300

Abstract:

A sample rate converter suitable for use in an audio DAC includes a first estimating circuit (A) generating first (TR) and second (STAMPR) signals synchronized to an asynchronous clock (MCLK) and representing the period and edge arrival times, respectively, of a reference clock (REFCLK). A second estimating circuit (B) operates on the first and second signals to generate third (T) and fourth (STAMP) signals representing an input sample rate (32fsin) and arrival times of input data samples, respectively, which are applied to a coefficient and address generator () to generate read addresses and coefficients input to a FIFO memory () receiving digital input data at the input sample rate and a multiplication/accumulation circuit () receiving data from the FIFO memory. The multiplication/accumulation circuit produces an output signal (SRC-out) synchronized to the asynchronous clock at an output sample rate (32fsout).

US Patent:

7733151, Jun 8, 2010

Filed:

Dec 8, 2008

Appl. No.:

12/316166

Inventors:

Shawn Xianggang Yu - Austin TX, US
Terry L. Sculley - Lewisville TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 3/00

US Classification:

327291, 327156

Abstract:

A clock signal generator () includes a phase locked loop (PLL) circuit () which requires a reference clock signal of at least a predetermined first frequency (f). A first clock signal (REFCLK) of a second frequency (f) that is substantially lower than the first frequency (f) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (f) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (), which produces an output clock signal (PLLCLK or CLKOUT).

US Patent:

8438036, May 7, 2013

Filed:

Sep 3, 2009

Appl. No.:

12/553713

Inventors:

Shawn X. Yu - Austin TX, US
Terry L. Sculley - Lewisville TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G10L 19/00

US Classification:

704500, 704503, 704200

Abstract:

In recent years, it has become commonplace for portable devices to generate analog audio signals from numerous sources, meaning that the codecs employed in these portable devices need to be able to utilize various digital bit streams at different sampling rates. To date, however, the circuitry for asynchronous sampling rate conversions for multiple bit streams has been complex, rigid, and power hungry. Here, a codec is provided which uses miniDSP cores to perform asynchronous sampling rate conversion efficiently and with reduced power consumption compared to other conventional codecs.

US Patent:

20200266800, Aug 20, 2020

Filed:

May 5, 2020

Appl. No.:

16/867331

Inventors:

- Dallas TX, US
Shawn Xianggang YU - Tucson AZ, US

International Classification:

H03H 17/06
H03M 3/00

Abstract:

Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.

US Patent:

20190273482, Sep 5, 2019

Filed:

Sep 14, 2018

Appl. No.:

16/132337

Inventors:

- Dallas TX, US
Shawn Xianggang YU - Tucson AZ, US

International Classification:

H03H 17/06
H03M 3/00

Abstract:

Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.