Sherry E Moore

US Patent:

7882319, Feb 1, 2011

Filed:

Sep 27, 2007

Appl. No.:

11/863160

Inventors:

Darrin P. Johnson - San Jose CA, US
Eric C. Saxe - Livermore CA, US
Sherry Q. Moore - Fremont CA, US

Assignee:

Oracle America Inc. - Redwood City CA

International Classification:

G06F 13/00
G06F 13/28

US Classification:

711165, 711170, 711173, 711E12041

Abstract:

A method for memory management that includes receiving a request for memory space, identifying a first memory module from a plurality of memory modules based on a first memory power management policy, wherein the first memory power management policy specifies how to allocate memory space in the plurality of memory modules to satisfy a power consumption criteria, and allocating the memory space on the first memory module.

US Patent:

7979648, Jul 12, 2011

Filed:

May 30, 2008

Appl. No.:

12/130491

Inventors:

Eric C. Saxe - Livermore CA, US
Sherry Q. Moore - Fremont CA, US
Darrin P. Johnson - San Jose CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 12/00

US Classification:

711157, 711158

Abstract:

Methods and apparatus provide for a Dynamic Interleaver to modify the interleaving distribution spanning physical memory modules. Specifically, dynamic interleaving provides the ability to increase the number of interleaved physical memory modules when a current interleaved group of memory locations is experiencing heavy use. By increasing the number of interleaved memory locations, a system can make optimal use of memory by allowing more parallel accesses to physical memory during the period of heavy utilization. However, if the current interleaved group of memory locations experience low use, the Dynamic Interleaver can choose to interleave across fewer physical memory modules and apply power management techniques to those memory locations that are no longer being accessed. Prior to “re-interleaving” interleaved memory locations, the Dynamic Interleaver migrates data out of the current interleaved memory locations. After re-interleaving, the Dynamic Interleaver maps the data back into the re-interleaved memory locations.

US Patent:

8516237, Aug 20, 2013

Filed:

Jan 12, 2010

Appl. No.:

12/686203

Inventors:

Sherry Qianhong Moore - Fremont CA, US
Konstantin Ananyev - Naas, IE
Darrin P. Johnson - San Jose CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 15/177

US Classification:

713100, 713 1, 713 2, 714 1, 714 25

Abstract:

A method for transferring execution to a subsequent operating system. The method includes rebooting a computer system. Rebooting the computer system includes initializing an in-kernel boot loader. The in-kernel boot loader executes in a kernel of an initial operating system. Rebooting the computer system further includes populating, by the in-kernel boot loader, an initialization data structure using system data gathered during the execution of the initial operating system, loading, by the in-kernel boot loader, the subsequent operating system, and transferring control of the computer system from the initial operating system to the subsequent operating system. The subsequent operating system accesses the initialization data structure to identify available hardware. The method further includes executing the subsequent operating system on the available hardware of the computer system.

US Patent:

20190370659, Dec 5, 2019

Filed:

Aug 14, 2019

Appl. No.:

16/540558

Inventors:

- Mountain View CA, US
Sherry Moore - Los Altos CA, US
Esteban Alberto Real - Sunnyvale CA, US
Thomas M. Breuel - Sparks NV, US

International Classification:

G06N 3/08
G06N 20/00
G06K 9/62
G06F 11/34

Abstract:

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for optimizing neural network architectures. One of the methods includes receiving training data; determining, using the training data, an optimized neural network architecture for performing the machine learning task; and determining trained values of parameters of a neural network having the optimized neural network architecture.