Shilong E Zhang

US Patent:

6359512, Mar 19, 2002

Filed:

Jan 18, 2001

Appl. No.:

09/765267

Inventors:

Vadim V. Ivanov - Tucson AZ
Shilong Zhang - Tucson AZ
Gregory H. Johnson - Tucson AZ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 345

US Classification:

330255, 330264, 330267

Abstract:

An operational amplifier includes a differential input stage ( ) having first ( ) and second ( ) input conductors, a class AB output stage ( ) coupled to an output of the differential input stage ( ) and including a pull-up transistor (M ) having a source coupled to a first supply voltage (V ), a drain coupled to an output conductor ( ), and a gate coupled to a first terminal ( ) of a class AB control circuit ( ), and a pull-down transistor (M ) having a source coupled to a second supply voltage (GND), a drain coupled to the output conductor ( ), and a gate coupled to a second terminal ( ) of the class AB control circuit ( ). A differential input signal is applied between the first ( ) and second ( ) input conductors, and simultaneously also is applied between first and second inputs of a first unbalanced differential amplifier ( ) and between first and second input to the second unbalanced differential amplifier ( ). If the differential input signal is of a first polarity and is of a magnitude substantially greater than a threshold voltage of the first unbalanced differential amplifier ( ), the magnitude of a turn-on voltage of the pull-down transistor (M ) is decreased and the magnitude of a turn-on voltage of the pull-up transistor (M ) is increased in response to an output voltage produced by the first unbalanced differential amplifier ( ). However, if the differential input signal is of a second polarity and is of a magnitude substantially greater than a threshold voltage of the second unbalanced differential amplifier ( ), then the magnitude of a turn-on voltage of the pull-up transistor (M ) is increased and the magnitude of a turn-on voltage of the pull-down transistor (M ) is simultaneously decreased, in response to an output voltage produced by the second unbalanced differential amplifier ( ).

US Patent:

6400207, Jun 4, 2002

Filed:

Apr 3, 2001

Appl. No.:

09/825401

Inventors:

Vadim V. Ivanov - Tucson AZ
Shilong Zhang - Tucson AZ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03L 700

US Classification:

327374, 327376, 327377, 323901

Abstract:

Bias circuitry of an electronic circuit is disabled by interrupting a compensated feedback loop in a bias control circuit that, when enabled, produces a predetermined bias voltage (V ) applied to the bias circuitry. A trickle charging current is conducted into a compensation capacitor of the feedback loop while the bias circuitry is disabled, to charge the compensation capacitor to a predetermined threshold voltage which causes the feedback loop and bias control circuit, when enabled, to produce the predetermined voltage needed by the bias circuitry to bias the CMOS operational amplifier for normal operation. Next, the feedback loop is enabled. Since the compensation capacitor is already precharged to the predetermined voltage, the bias circuitry of the CMOS operational amplifier is very quickly enabled from the disabled condition.

US Patent:

6462619, Oct 8, 2002

Filed:

Jan 8, 2001

Appl. No.:

09/756259

Inventors:

Vadim V. Ivanov - Tucson AZ
Shilong Zhang - Tucson AZ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 345

US Classification:

330253, 330257

Abstract:

An input to a rail-to-rail, FET, operational amplifier having a transconductance that is constant throughout the operating range of the operational amplifier is presented. The input of an operational amplifier typically includes an input stage, a current source and a current transfer circuit, wherein the input stage comprises both N-type transistors and P-type transistors. The present application discloses the use of a duplicate of those elements: a proportional input stage, a proportional current source, and a proportional current transfer circuit, which together are used to emulate the operation of the input stage. By monitoring these proportional duplicates, one can determine when both input pairs are operating. When both input pairs are operating, a minimum selector circuit interfaces with the current transfer circuit to reduce the current supplying one of the input pair transistors, thus reducing the overall transconductance of the circuit.

US Patent:

6703900, Mar 9, 2004

Filed:

Jun 5, 2002

Appl. No.:

10/163113

Inventors:

Vadim V. Ivanov - Tucson AZ
Shilong Zhang - Tucson AZ
Gregory H. Johnson - Tucson AZ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 152

US Classification:

330255, 330264, 330267

Abstract:

A differential amplifier includes an input stage ( ) and an output stage ( ) including an output transistor (M ) having a source coupled to a supply voltage (V ), a gate coupled to a terminal ( ) of the input stage, and a drain coupled to an output conductor ( ). A recovery circuit ( A) is coupled between the supply voltage and the gate of the output transistor for limiting the voltage on the gate of the output transistor in response to the output voltage be within a predetermined range of the supply voltage and includes a recovery transistor (M ) with a source coupled to the output conductor and a drain coupled to the gate of the output transistor and a common-gate amplifier ( A) having a built-in offset a first input coupled to the output conductor, a second input coupled to the supply voltage, and an output coupled to the gate of the recovery transistor.

US Patent:

63170000, Nov 13, 2001

Filed:

Jan 18, 2001

Appl. No.:

9/765485

Inventors:

Vadim V. Ivanov - Tucson AZ
Shilong Zhang - Tucson AZ
Gregory H. Johnson - Tucson AZ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 345

US Classification:

330255

Abstract:

An operational amplifier includes an input stage (13) receiving an input signal (Vin) and having first (14) and second (16) output terminals, and also includes an output stage (10) having a pull-up transistor (M11) and a pull-down transistor (M2). The pull-up transistor has a source coupled to a first supply voltage (V. sub. DD), a gate coupled to the first output terminal (14), and a drain coupled to an output conductor (22) conducting an output signal (Vout). The pull-down transistor (M2) has a source coupled to a second supply voltage (V. sub. SS), a gate coupled to the second output terminal (16), and a drain coupled to the output conductor (22). An AB control circuit (20) is coupled between the gates of the pull-up transistor and a pull-down transistor. A first overload recovery circuit (X) is coupled between the output conductor (22) and the gate of the pull-up transistor for limiting the voltage on the gate of the pull-up transistor in response to the output voltage (Vout) when the output voltage is within a first predetermined range of the first supply voltage (V. sub. DD). A second overload recovery circuit (Y) is coupled between the output conductor (22) and the gate of the pull-down transistor for limiting the voltage on the gate of the pull-down transistor in response to the output voltage (Vout) when the output voltage is within a second predetermined range of the second supply voltage (V. sub. SS).