Shrenik M Mehta

US Patent:

6499123, Dec 24, 2002

Filed:

Apr 12, 2000

Appl. No.:

09/547981

Inventors:

Harold L. McFarland - Los Gatos CA
David R. Stiles - Los Gatos CA
Korbin S. Van Dyke - Fremont CA
Shrenik Mehta - San Jose CA
John Gregory Favor - San Jose CA
Dale R. Greenley - Los Gatos CA
Robert A. Cargnoni - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H04B 1700

US Classification:

714724, 714718

Abstract:

An integrated circuit having a normal mode for operating under normal operating conditions and a debug mode for operating to test and debug the integrated circuit. The integrated circuit includes a plurality of output pins that carry a first plurality of signals in the normal mode and carry a second plurality of signals in the debug mode. In one embodiment, the integrated circuit embodies a microprocessor. The microprocessor may include logic circuitry for enabling the second plurality of signals to be output from a multiplexer to the output pins in response to a predetermined event, such as a hit in an associated memory unit.

US Patent:

7475369, Jan 6, 2009

Filed:

Mar 18, 2005

Appl. No.:

11/083805

Inventors:

William K. Lam - Newark CA, US
Shrenik M. Mehta - San Jose CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 5, 716 4, 716 18, 703 13, 703 14

Abstract:

Techniques are disclosed for automatically determining whether a potential constraint set to be applied to a portion of a circuit are overconstrained. An environment circuit supplies inputs to the circuit portion. Embodiments of the invention recognize that if the environment circuit produces a set of outputs that contain a pattern that is not present in the potential constraint set, then the potential constraint set is overconstrained. A verification tool establishes the properties for the environmental circuit based on the potential constraint set. If the verification tool determines that the outputs produced by the environment circuit conflict with the properties of the environment circuit, then the verification tool concludes that the potential constraint set is overconstrained, because the environment circuit produces a pattern that is not present in the potential constraint set. Advantageously, the laborious and error-prone process of manually determining the proper inputs to apply during formal verification is avoided.

US Patent:

52261263, Jul 6, 1993

Filed:

Feb 21, 1990

Appl. No.:

7/483223

Inventors:

Harold L. McFarland - San Jose CA
David R. Stiles - Sunnyvale CA
Korbin S. Van Dyke - Fremont CA
Shrenik Mehta - San Jose CA
John G. Favor - San Jose CA
Dale R. Greenley - San Jose CA
Robert A. Cargnoni - Sunnyvale CA

Assignee:

Nexgen Microsystems - San Jose CA

International Classification:

G06F 938
G06F 1576

US Classification:

395375

Abstract:

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

US Patent:

54427576, Aug 15, 1995

Filed:

Mar 3, 1993

Appl. No.:

8/025439

Inventors:

Harold L. McFarland - San Jose CA
David R. Stiles - Sunnyvale CA
Korbin S. Van Dyke - Fremont CA
Shrenik Mehta - San Jose CA
John G. Favor - San Jose CA
Dale R. Greenley - San Jose CA
Robert A. Cargnoni - Sunnyvale CA

Assignee:

NexGen, Inc. - Milpitas CA

International Classification:

G06F 1516

US Classification:

395375

Abstract:

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

US Patent:

57817537, Jul 14, 1998

Filed:

Mar 13, 1995

Appl. No.:

8/403988

Inventors:

Harold L. McFarland - Los Gatos CA
David R. Stiles - Los Gatos CA
Korbin S. Van Dyke - Fremont CA
Shrenik Mehta - San Jose CA
John Gregory Favor - San Jose CA
Dale R. Greenley - Los Gatos CA
Robert A. Cargnoni - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G06F 938

US Classification:

395394

Abstract:

A pipeline control system for implementing a virtual architecture having a complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These operations, each having an associated tag, are issued to the functional units. Address processing unit computes addresses of the instructions and operands, performs segment relocation, and manages the processor's memory. Operations are executed by the units in a manner that is generally independent of operation processing by the other units. The units report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. Thus, the functional units enable multiple operations to be executed in a speculative and out-of-order manner to fully utilize the resources of the processor.

US Patent:

62126296, Apr 3, 2001

Filed:

Jul 14, 1998

Appl. No.:

9/115165

Inventors:

Harold L. McFarland - Los Gatos CA
David R. Stiles - Los Gatos CA
Korbin S. Van Dyke - Fremont CA
Shrenik Mehta - San Jose CA
John Gregory Favor - San Jose CA
Dale R. Greenley - Los Gatos CA
Robert A. Cargnoni - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 930

US Classification:

712241

Abstract:

A pipeline control system for implementing a virtual architecture having a complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These operations, each having an associated tag, are issued to the functional units. Address processing unit computes addresses of the instructions and operands, performs segment relocation, and manages the processor's memory. Operations are executed by the units in a manner that is generally independent of operation processing by the other units. The units report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. Thus, the functional units enable multiple operations to be executed in a speculative and out-of-order manner to fully utilize the resources of the processor.

US Patent:

56824920, Oct 28, 1997

Filed:

Jan 30, 1995

Appl. No.:

8/380736

Inventors:

Harold L. McFarland - San Jose CA
David R. Stiles - Sunnyvale CA
Korbin S. Van Dyke - Fremont CA
Shrenik Mehta - San Jose CA
John Gregory Favor - San Jose CA
Dale R. Greenley - San Jose CA
Robert A. Cargnoni - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 930

US Classification:

395390

Abstract:

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

US Patent:

57685754, Jun 16, 1998

Filed:

Mar 13, 1995

Appl. No.:

8/405272

Inventors:

Harold L. McFarland - Los Gatos CA
David R. Stiles - Los Gatos CA
Korbin S. Van Dyke - Fremont CA
Shrenik Mehta - San Jose CA
John Gregory Favor - San Jose CA
Dale R. Greenley - Los Gatos CA
Robert A. Cargnoni - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 930

US Classification:

395569

Abstract:

A pipeline control system for implementing a virtual architecture having complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These operations, each having an associated tag, are issued to the functional units. Address processing unit computes addresses of the instructions and operands, performs segment relocation, and manages the processor's memory. Operations are executed by the units in a manner that is generally independent of operation processing by the other units. The units report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. Thus, the functional units enable multiple operations to be executed in a speculative and out-of-order manner to fully utilize the resources of the processor.