Siamak N Tavallaei

US Patent:

6360291, Mar 19, 2002

Filed:

Feb 1, 1999

Appl. No.:

09/241203

Inventors:

Siamak Tavallaei - Spring TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1314

US Classification:

710129, 710126, 710104, 710100, 710 8

Abstract:

A computer system with an Intelligent Input/Output architecture having a dynamic device blocking mechanism for hiding at least a portion of peripheral devices. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. A plurality of I/O bus signals are supplied to the device blocking module for determining which bus master owns the I/O bus in order to initiate a bus cycle. If the bus cycle is about to be commenced on behalf of the host processor and its OS, an enable signal associated with the selected peripheral device is negated until the cycle is completed. If, on the other hand, the bus cycle is initiated by the IOP, the enable signal is asserted for the duration of the transaction, which signal, otherwise, remains in a negated state.

US Patent:

6385682, May 7, 2002

Filed:

May 17, 1999

Appl. No.:

09/313220

Inventors:

Theodore F. Emerson - Houston TX
Siamak Tavallaei - Spring TX
John V. Butler - The Woodlands TX

Assignee:

Compaq Information Technologies, Group, L.P. - Houston TX

International Classification:

G06F 1516

US Classification:

710260, 710 48, 710129, 709219

Abstract:

A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality assist logic structure for effectuating the sending and receiving-of signals from the remote terminal. The remote console functionality assist logic structure is controlled by a dedicated processor that receives interrupts therefrom in response to a remote management application. The processor can also control one or more peripheral devices provided in the computer system, wherein the controlled peripheral device or devices are disposed up-stream or down-stream from the processor.

US Patent:

6438627, Aug 20, 2002

Filed:

May 12, 1998

Appl. No.:

09/076561

Inventors:

Brian S. Hausauer - Spring TX
Siamak Tavallaei - Spring TX

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 1314

US Classification:

710 35, 710 33, 710305, 710300, 711204, 711213

Abstract:

An apparatus is disclosed for predicting and making available in advance certain information, namely the address signals from an expansion bus, so as to relax the timing requirement of the burst transfer cycle. A decoder responds to the control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder controls a counter, which stores the initial address signals of the expansion bus at the start of the burst transfer cycle and predicts the initial address signals by incrementing the address signals during the burst transfer cycle. A multiplexer couples either the predicted address signal to the multiplexer output during the burst transfer cycle or the address signal of the EISA bus to the multiplexer output when the computer system is not performing the EMB burst transfer cycle. In another aspect of the present invention, the low order address signal of the bus is predicted using a second counter. The output of the second counter is merged into the low order address signal of the bus interface devices to properly index the second word of the burst transfer cycle.

US Patent:

6608564, Aug 19, 2003

Filed:

Jan 25, 2001

Appl. No.:

09/770100

Inventors:

Christian H. Post - Spring TX
George D. Megason - Spring TX
Brett D. Roscoe - Tomball TX
Paul Santeler - Cypress TX
John M. MacLaren - Cypress TX
John E. Larson - Houston TX
Jeffery Galloway - The Woodlands TX
Siamak Tavallaei - Spring TX
Tim W. Majni - Woodlands TX
Robert Allan Lester - Tomball TX
Anisha Anand - Houston TX
Eric Rose - Austin TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G08B 2300

US Classification:

3406935, 3406939, 34069312

Abstract:

A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

US Patent:

6742066, May 25, 2004

Filed:

Mar 27, 2002

Appl. No.:

10/108106

Inventors:

Theodore F. Emerson - Houston TX
Siamak Tavallaei - Spring TX
John V. Butler - The Woodlands TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1516

US Classification:

710260, 710 48, 710129, 709219

Abstract:

A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality assist logic structure for effectuating the sending and receiving of signals from the remote terminal. The remote console functionality assist logic structure is controlled by a dedicated processor that receives interrupts therefrom in response to a remote management application. The processor can also control one or more peripheral devices provided in the computer system, wherein the controlled peripheral device or devices are disposed up-stream or down-stream from the processor.

US Patent:

6747563, Jun 8, 2004

Filed:

May 14, 2003

Appl. No.:

10/437567

Inventors:

Christian H. Post - Spring TX
George D. Megason - Spring TX
Brett D. Roscoe - Tomball TX
Paul Santeler - Cypress TX
John M. MacLaren - Cypress TX
John E. Larson - Houston TX
Jeffery Galloway - The Woodlands TX
Siamak Tavallaei - Spring TX
Tim W. Majni - Woodlands TX
Robert Allan Lester - Tomball TX
Anisha Anand - Houston TX
Eric Rose - Austin TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G08B 2300

US Classification:

3406935, 3406939, 34069312

Abstract:

A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

US Patent:

6792490, Sep 14, 2004

Filed:

Nov 16, 2001

Appl. No.:

09/991058

Inventors:

Siamak Tavallaei - Spring TX

Assignee:

Hewlett-Packard Development, L.P. - Houston TX

International Classification:

G06F 1314

US Classification:

710129, 710126, 710104, 710100, 710 8

Abstract:

A computer system with an Intelligent Input/Output architecture having a dynamic device blocking mechanism for hiding at least a portion of peripheral devices. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. A plurality of I/O bus signals are supplied to the device blocking module for determining which bus master owns the I/O bus in order to initiate a bus cycle. If the bus cycle is about to be commenced on behalf of the host processor and its OS, an enable signal associated with the selected peripheral device is negated until the cycle is completed. If, on the other hand, the bus cycle is initiated by the IOP, the enable signal is asserted for the duration of the transaction, which signal, otherwise, remains in a negated state.

US Patent:

6975241, Dec 13, 2005

Filed:

May 14, 2003

Appl. No.:

10/438150

Inventors:

Christian H. Post - Spring TX, US
George D. Megason - Spring TX, US
Brett D. Roscoe - Tomball TX, US
Paul Santeler - Cypress TX, US
John M. MacLaren - Cypress TX, US
John E. Larson - Houston TX, US
Jeffery Galloway - The Woodlands TX, US
Siamak Tavallaei - Spring TX, US
Tim W. Majni - Woodlands TX, US
Robert Allan Lester - Tomball TX, US
Anisha Anand - Houston TX, US
Eric Rose - Austin TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G08B023/00

US Classification:

3406935, 3406939, 34069312

Abstract:

A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.