Sidhartha Gupta

US Patent:

20220302148, Sep 22, 2022

Filed:

Mar 18, 2021

Appl. No.:

17/205954

Inventors:

- Boise ID, US
Sidhartha Gupta - Boise ID, US
Kar Wui Thong - Boise ID, US
Harsh Narendrakumar Jain - Boise ID, US

International Classification:

H01L 27/11556
H01L 27/11582
G11C 5/06
H01L 29/66
H01L 29/78

Abstract:

A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.

US Patent:

20220270830, Aug 25, 2022

Filed:

Feb 19, 2021

Appl. No.:

17/179890

Inventors:

- Boise ID, US
Sidhartha Gupta - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01G 11/26
H01L 27/105
H01G 11/08
H01G 11/36
H01L 49/02
H01G 11/86

Abstract:

Some embodiments include an integrated assembly having a supercapacitor supported by a semiconductor substrate. The supercapacitor includes first and second electrode bases. The first electrode base includes first laterally-projecting regions, and the second electrode base includes second laterally-projecting regions which are interdigitated with the first laterally-projecting regions. A distance between the first and second laterally-projecting regions is less than or equal to about 500 nm. Carbon nanotubes extend upwardly from the first and second electrode bases. The carbon nanotubes are configured as a first membrane structure associated with the first electrode base and as a second membrane structure associated with the second electrode base. Pseudocapacitive material is dispersed throughout the first and second membrane structures. Electrolyte material is within and between the first and second membrane structures. Some embodiments include methods of forming integrated assemblies.

US Patent:

20220238431, Jul 28, 2022

Filed:

Jan 28, 2021

Appl. No.:

17/161313

Inventors:

- Boise ID, US
Sidhartha Gupta - Boise ID, US
Pankaj Sharma - Boise ID, US
Haitao Liu - Boise ID, US

International Classification:

H01L 23/522
H01L 27/11582
G11C 5/06
H01L 27/11556
H01L 21/768
H01L 21/48

Abstract:

A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

US Patent:

20220199641, Jun 23, 2022

Filed:

Dec 18, 2020

Appl. No.:

17/127971

Inventors:

- Boise ID, US
Jun Fujiki - Tokyo, JP
Matthew J. King - Boise ID, US
Sidhartha Gupta - Boise ID, US
Paolo Tessariol - Arcore, IT
Kunal Shrotri - Boise ID, US
Kye Hyun Baek - Boise ID, US
Kyle A. Ritter - Boise ID, US
Shuji Tanaka - Tokyo, JP
Umberto Maria Meotto - Rivoli, IT
Richard J. Hill - Boise ID, US
Matthew Holland - Boise ID, US

International Classification:

H01L 27/11582
H01L 27/11556

Abstract:

A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

US Patent:

20230045353, Feb 9, 2023

Filed:

Aug 9, 2021

Appl. No.:

17/396939

Inventors:

- Boise ID, US
Indra V. Chary - Boise ID, US
Anilkumar Chandolu - Boise ID, US
Sidhartha Gupta - Boise ID, US

International Classification:

H01L 23/528
H01L 27/11551
H01L 27/1157
H01L 27/11578
H01L 27/11524
H01L 23/522
H01L 23/532
H01L 21/768

Abstract:

A microelectronic device, including a stack structure including alternating conductive structures and dielectric structures is disclosed. Memory pillars extend through the stack structure. Contacts are laterally adjacent to the memory pillars and extending through the stack structure. The contacts including active contacts and support contacts. The active contacts including a liner and a conductive material. The support contacts including the liner and a dielectric material. The conductive material of the active contacts is in electrical communication with the memory pillars. Methods and electronic systems are also disclosed.