Simon S Chan

US Patent:

6335273, Jan 1, 2002

Filed:

Nov 19, 1999

Appl. No.:

09/443376

Inventors:

Richard J. Huang - Cupertino CA
Guarionex Morales - Santa Clara CA
Simon Chan - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438622, 438624, 438683, 438685, 438687, 257758

Abstract:

A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

US Patent:

6355575, Mar 12, 2002

Filed:

May 22, 2000

Appl. No.:

09/575463

Inventors:

Fei Wang - San Jose CA
Simon S. Chan - Saratoga CA
Susan Chen - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21302

US Classification:

438712

Abstract:

HSQ is employed as a dielectric layer in manufacturing a high density, multi-metal layer semiconductor device. The degradation of deposited HSQ layers during formation of the semiconductor device, as from photoresist stripping using an O -containing plasma, is avoided by forming first and second dielectric layers on the HSQ layer, forming a photoresist mask on the second dielectric layer and etching to form an opening in the second dielectric layer leaving the first dielectric layer exposed. The first dielectric layer protects the HSQ from degradation during subsequent stripping.

US Patent:

6368949, Apr 9, 2002

Filed:

Sep 21, 2000

Appl. No.:

09/666342

Inventors:

Susan H. Chen - Santa Clara CA
Simon S. Chan - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 213205

US Classification:

438592, 438774

Abstract:

Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices have been reduced or a minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include forming a sacrificial oxide and removing the sacrificial oxide to remove the carbonaceous residues and anneal out damage to the silicon substrate. Subsequently formed silicide regions on the source and drain regions have improved quality.

US Patent:

6417571, Jul 9, 2002

Filed:

Mar 1, 2000

Appl. No.:

09/516343

Inventors:

Takeshi Nogami - Sunnyvale CA
Simon Chan - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348

US Classification:

257762, 257520, 257521, 257751

Abstract:

A system and method for providing copper interconnect in a trench formed in a dielectric is disclosed. In one aspect, the method and system include providing a copper layer; removing a portion of the copper layer outside of the trench; annealing the copper layer; and providing a layer disposed above the copper layer. In another aspect, the method and system include providing a copper interconnect formed in a trench on a dielectric. The copper interconnect includes a copper layer disposed in the trench and a layer disposed above the copper layer. The copper layer has a bamboo structure at least one grain. The at least one grain has substantially one orientation.

US Patent:

6472317, Oct 29, 2002

Filed:

Feb 12, 2001

Appl. No.:

09/780457

Inventors:

Fei Wang - San Jose CA
Jerry Cheng - Milpitas CA
Simon S. Chan - Saratoga CA
Todd Lukanc - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438638, 438637, 438624, 438738

Abstract:

A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A second low k dielectric layer is formed on the first low k dielectric layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Further etching of the first dielectric layer is prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

US Patent:

6518173, Feb 11, 2003

Filed:

Aug 17, 2000

Appl. No.:

09/640081

Inventors:

Simon S. Chan - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438637, 438627, 438628

Abstract:

Corrosion and degradation of tantalum-based adhesion/barrier layers used in multi-level semiconductor devices employing copper-based interconnect metallization systems are avoided or minimized. In embodiments of the present invention, deleterious fluorine-containing contaminants formed on underlying copper-based metal features as a result of etching through-holes in silicon-based interlevel dielectric material layers for via holes is prevented by the use of fluorine-free etching processes. Other embodiments of the present invention include performing a two-step etching sequence comprising a first, fluorine-containing process and a second, fluorine-free process.

US Patent:

6537866, Mar 25, 2003

Filed:

Oct 18, 2000

Appl. No.:

09/691643

Inventors:

Jeffrey A. Shields - Sunnyvale CA
Tuan D. Pham - San Jose CA
Jusuke Ogura - Cupertino CA
Bharath Rangarajan - Santa Clara CA
Simon Siu-Sing Chan - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 21338

US Classification:

438183, 438230, 438780, 438197, 438585, 438412, 430 14, 430 18, 430313

Abstract:

A method for forming insulating spacers for separating conducting layers in semiconductor wafer fabrication. The spacers are formed by removing portions of a protective photoresist layer through photolithography, and then through etching of exposed portions of the insulating layer. The spacers allow for fabrication of components that are smaller in size than are obtainable through conventional photolithography methods.

US Patent:

6624476, Sep 23, 2003

Filed:

Apr 29, 2002

Appl. No.:

10/134973

Inventors:

Simon Siu-Sing Chan - Saratoga CA
Matthew S. Buynoski - Palo Alto CA
Qi Xiang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2900

US Classification:

257347, 257348, 257349, 257350, 257351, 257352, 257353, 257354

Abstract:

A semiconductor-on-insulator (SOI) device includes a buried insulator layer and an overlying semiconductor layer. Portions of the insulator layer are doped with the same dopant material, for example boron, as is in corresponding portions of the overlying surface semiconductor layer. A peak concentration of the dopant material may be located in the insulator material, or may be located in a lower portion of the surface semiconductor layer. The dopant material in the insulator layer may prevent depletion of dopant material from portions of the surface semiconductor layer, such as from channel portions of NMOS transistors.